EFM32WG Datasheet, PDF (485/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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17.5.18 USARTn_IFS - Interrupt Flag Set Register
Offset
0x044
Reset
Access
Bit Position
Name
Bit
31:13
12
11
10
9
8
7
6
5
4
3
2:1
0
Name
Reset
Access Description
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
CCF
0
W1
Set Collision Check Fail Interrupt Flag
Write to 1 to set the CCF interrupt flag.
SSM
0
W1
Set Slave-Select in Master mode Interrupt Flag
Write to 1 to set the SSM interrupt flag.
MPAF
0
W1
Set Multi-Processor Address Frame Interrupt Flag
Write to 1 to set the MPAF interrupt flag.
FERR
0
W1
Set Framing Error Interrupt Flag
Write to 1 to set the FERR interrupt flag.
PERR
0
W1
Set Parity Error Interrupt Flag
Write to 1 to set the PERR interrupt flag.
TXUF
0
W1
Set TX Underflow Interrupt Flag
Write to 1 to set the TXUF interrupt flag.
TXOF
0
W1
Set TX Overflow Interrupt Flag
Write to 1 to set the TXOF interrupt flag.
RXUF
0
W1
Set RX Underflow Interrupt Flag
Write to 1 to set the RXUF interrupt flag.
RXOF
0
W1
Set RX Overflow Interrupt Flag
Write to 1 to set the RXOF interrupt flag.
RXFULL
0
W1
Set RX Buffer Full Interrupt Flag
Write to 1 to set the RXFULL interrupt flag.
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
TXC
0
W1
Set TX Complete Interrupt Flag
Write to 1 to set the TXC interrupt flag.
17.5.19 USARTn_IFC - Interrupt Flag Clear Register
Offset
0x048
Reset
Access
Bit Position
Name
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
485
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