EFM32WG Datasheet, PDF (508/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

...the world's most energy friendly microcontrollers
Bit
Name
Reset
Access Description
1
RXDIS
0
W1
Receiver Disable
Set to disable data reception. If a frame is under reception when the receiver is disabled, the incoming frame is discarded.
0
RXEN
0
W1
Receiver Enable
Set to activate data reception on LEUn_RX.
19.5.3 LEUARTn_STATUS - Status Register
Offset
0x008
Reset
Access
Bit Position
Name
Bit
Name
Reset
Access Description
31:6
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
5
RXDATAV
0
R
RX Data Valid
Set when data is available in the receive buffer. Cleared when the receive buffer is empty.
4
TXBL
1
R
TX Buffer Level
Indicates the level of the transmit buffer. Set when the transmit buffer is empty, and cleared when it is full.
3
TXC
0
R
TX Complete
Set when a transmission has completed and no more data is available in the transmit buffer. Cleared when a new transmission starts.
2
RXBLOCK
0
R
Block Incoming Data
When set, the receiver discards incoming frames. An incoming frame will not be loaded into the receive buffer if this bit is set at the
instant the frame has been completely received.
1
TXENS
0
R
Transmitter Enable Status
Set when the transmitter is enabled.
0
RXENS
0
R
Receiver Enable Status
Set when the receiver is enabled. The receiver must be enabled for start frames, signal frames, and multi-processor address bit
detection.
19.5.4 LEUARTn_CLKDIV - Clock Control Register (Async Reg)
For more information about Asynchronous Registers please see Section 5.3 (p. 21) .
Offset
0x00C
Bit Position
Reset
Access
Name
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
508
www.energymicro.com