EFM32WG Datasheet, PDF (57/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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9. The controller performs four DMA transfers.
10.The controller arbitrates. After the controller receives a request for this channel, the flow
continues if the channel has the highest priority.
11.The controller performs the remaining four DMA transfers.
12.The controller sets dma_done[C] HIGH for one HFCORECLK cycle and enters the
arbitration process.
After task B completes, the host processor can configure the alternate data structure for task D.
After the controller receives a new request for the channel and it has the highest priority then task C
commences:
Task C
13.The controller performs two DMA transfers.
14.The controller sets dma_done[C] HIGH for one HFCORECLK cycle and enters the
arbitration process.
After task C completes, the host processor can configure the primary data structure for task E.
After the controller receives a new request for the channel and it has the highest priority then task D
commences:
Task D
15.The controller performs four DMA transfers.
16.The controller arbitrates. After the controller receives a request for this channel, the flow
continues if the channel has the highest priority.
17.The controller performs the remaining DMA transfer.
18.The controller sets dma_done[C] HIGH for one HFCORECLK cycle and enters the
arbitration process.
After the controller receives a new request for the channel and it has the highest priority then task E
commences:
Task E
19.The controller performs four DMA transfers.
20.The controller arbitrates. After the controller receives a request for this channel, the flow
continues if the channel has the highest priority.
21.The controller performs the remaining three DMA transfers.
22.The controller sets dma_done[C] HIGH for one HFCORECLK cycle and enters the
arbitration process.
If the controller receives a new request for the channel and it has the highest priority then it attempts to
start the next task. However, because the host processor has not configured the alternate data structure,
and on completion of task D the controller set the cycle_ctrl bits to b000, then the ping-pong DMA
transaction completes.
Note
You can also terminate the ping-pong DMA cycle in Figure 8.3 (p. 56) , if you configure
task E to be a basic DMA cycle by setting the cycle_ctrl field to 3’b001.
8.4.2.3.5 Memory scatter-gather
In memory scatter-gather mode the controller receives an initial request and then performs four DMA
transfers using the primary data structure. After this transfer completes, it starts a DMA cycle using the
alternate data structure. After this cycle completes, the controller performs another four DMA transfers
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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