EFM32WG Datasheet, PDF (431/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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Many slave-only devices operating on an I²C-bus are not capable of driving SCL low, but in the rare
case that SCL is stuck LOW, the advice is to apply a hardware reset signal to the slaves on the bus. If
this does not work, cycle the power to the devices in order to make them release SCL.
When SDA is stuck low and SCL is free, a master should send 9 clock pulses on SCL while tristating
the SDA. This procedure is performed in the GPIO module after clearing the I2C_ROUTE register and
disabling the I2C module. The device that held the bus low should release it sometime within those 9
clocks. If not, use the same approach as for when SCL is stuck, resetting and possibly cycling power
to the slaves.
Lockup of SDA can be detected by keeping count of the number of continuous arbitration losses during
address transmission. If arbitration is also lost during the transmission of a general call address, i.e.
during the transmission of the STOP condition, which should never happen during normal operation,
this is a good indication of SDA lockup.
Detection of SCL lockups can be done using the timeout functionality defined in Section 16.3.12.6 (p.
431)
16.3.12.5 Bus Idle Timeout
When SCL has been high for a significant amount of time, this is a good indication of that the bus is
idle. On an SMBus system, the bus is only allowed to be in this state for a maximum of 50 µs before
the bus is considered idle.
The bus idle timeout BITO in I2Cn_CTRL can be used to detect situations where the bus goes idle in the
middle of a transmission. The timeout can be configured in BITO, and when the bus has been idle for the
given amount of time, the BITO interrupt flag in I2Cn_IF is set. The bus can also be set idle automatically
on a bus idle timeout. This is enabled by setting GIBITO in I2Cn_CTRL.
When the bus idle timer times out, it wraps around and continues counting as long as its condition is
true. If the bus is not set idle using GIBITO or the ABORT command in I2Cn_CMD, this will result in
periodic timeouts.
Note
This timeout will be generated even if SDA is held low.
The bus idle timeout is active as long as the bus is busy, i.e. BUSY in I2Cn_STATUS is set. The timeout
can be used to get the I²C module out of the busy-state it enters when reset, see Section 16.3.7.3 (p.
421) .
16.3.12.6 Clock Low Timeout
The clock timeout, which can be configured in CLTO in I2Cn_CTRL, starts counting whenever SCL goes
low, and times out if SCL does not go high within the configured timeout. A clock low timeout results in
CLTOIF in I2Cn_IF being set, allowing software to take action.
When the timer times out, it wraps around and continues counting as long as SCL is low. An SCL lockup
will thus result in periodic clock low timeouts as long as SCL is low.
16.3.13 DMA Support
The I²C module has full DMA support. The DMA controller can write to the transmit buffer using the
I2Cn_TXDATA register, and it can read from the receive buffer using the RXDATA register. A request
for the DMA controller to read from the I²C receive buffer can come from the following source:
• Data available in the receive buffer
A write request can come from one of the following sources:
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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