EFM32WG Datasheet, PDF (266/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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3. The Non-periodic Request Queue depth = 4.
15.4.3.6.8.1 Normal Bulk and Control IN Operations
The sequence of operations in Figure 15.13 (p. 263) is as follows:
1. Initialize and enable channel 2 as explained in Channel Initialization (p. 252) .
2. The host writes an IN request to the Request queue as soon as channel 2 receives the grant from
the arbiter. (Arbitration is performed in a round-robin fashion, with fairness.).
3. The host starts writing the received data to the system memory as soon as the last byte is received
with no errors.
4. When the last packet is received, the host sets an internal flag to remove any extra IN requests from
the Request queue.
5. The host flushes the extra requests.
6. The final request to disable channel 2 is written to the Request queue. At this point, channel 2 is
internally masked for further arbitration.
7. The host generates the CHHLTD interrupt as soon as the disable request comes to the top of the
queue.
8. In response to the CHHLTD interrupt, de-allocate the channel for other transfers.
15.4.3.6.8.2 Handling Interrupts
The channel-specific interrupt service routine for bulk and control IN transactions in DMA mode is shown
in the following flow:
Interrupt Service Routines for Bulk/Control Bulk/Control IN Transactions in DMA Mode
Bulk/Control IN
Unmask (CHHLTD)
if (CHHLTD)
{
if (XFERCOMPL or STALL or BBLERR)
{
Reset Error Count Mask ACK De-allocate Channel
}
else if (XACTERR)
{
if (Error_count == 2)
{
De-allocate Channel
}
else
{
Unmask ACK
Unmask NAK
Unmask DATATGLERR
Increment Error
Count Re-initialize Channel
}
}
}
else if (ACK or NAK or DATATGLERR)
{
Reset Error Count
Mask ACK
Mask NAK
Mask DATATGLERR
}
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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