English
Language : 

EFM32WG Datasheet, PDF (728/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.
...the world's most energy friendly microcontrollers
Figure 30.3. Opamp Output Stage Overview
+
OPA0
-
OPA0
output
OPA0 Main out put
MAIN/ALL
OPA0 Alt ernat ive
output network
+
OPA1
-
OPA1
output
OUT0
OUT1
OUT2
OUT3
OUT4
NEXTOUT
ADC CH0
input mux
OPA1 Main out put
MAIN/ALL
OPA1 Alt ernat ive
output network
+
OPA2
-
OPA2
output
OUT0
OUT1
OUT2
OUT3
OUT4
NEXTOUT
ADC CH1
input mux
MAIN
OPA2 Main out put s
OUT0
ADC CH5
input mux
OUT1
ADC CH0
input mux
The alternative output network consists of connections to pins, ADC, and a connection to the next opamp
(OPA0 to OPA1, and OPA1 to OPA2). The connections to pins can be individually enabled by configuring
OUTPEN in DACn_OPAxMUX register. To enable cascaded opamp configurations, each opamp has a
NEXTOUT connection. This output makes it possible to connect OPA0 to OPA1, and OPA1 to OPA2.
This output connection is enabled by setting NEXTOUT in DACn_OPAxMUX.
The opamps can also be routed to the ADC. OPA0 can be connected to ADC CH0, OPA1 to ADC CH1
and OPA2 can be connected to both ADC CH1 and CH5. The ADC connections are created by routing
the OPA output by setting corresponding bits in OUTPEN in DACn_OPAxMUX. For OPA0 alternative
output 4 is connected to ADC input mux CH0 when enabled. OPA1's alternative output 4 is connected
to ADC input mux CH1 when enabled. For OPA2, the two main outputs can be connected to ADC input
mux CH0 and ADC input mux CH5 respectively when enabled. See Section 28.3.4 (p. 684) , in the ADC
chapter for information on how to configure the ADC input mux.
30.3.1.3 Gain Programming
The feedback path of each mux includes a resistor ladder, which can be used to select a set of gain
values. The gain can be selected by the RESSEL bit-field located in DACn_OPAxMUX register. The
gain values are taken from tappings of the resistor ladder based on ratio of R2/R1. It is also possible to
bypass the resistor ladder in Unity Gain (UG) mode.
30.3.1.4 Offset Calibration
The offset calibration registers are located in different registers for the opamps. OPA0 and OPA1's offset
can be set through the CH0OFFSET and CH1OFFSET bit-fields respectively in DACn_CAL. The offset
for OPA2 can be set through OPA2OFFSET in DACn_OPAOFFSET.
30.3.1.5 Shorting Non-inverting and Inverting Input
Functionality for offset calibration of the opamps has been added, this functionality is enabled by
setting the OPAxSHORT bit-field in DACn_OPAxCTRL. Setting this bit-field enables a switch that shorts
between the inverting and non-inverting input of the OPA, effectively driving the offset voltage of the
opamp to the output. Using the ADC to measure this offset, the calibration register can be adjusted to
minimize the output offset.
30.3.1.6 Low Pass Filter
The low pass filter is located between the pad and the positive input. The low-pass filter is designed to
couple the input signal to local VSS for high frequencies and has a 3 dB frequency of approximately 130
MHz when driven from a 50 ohm source. The filter adds a parasitic capacitance of approximately 1.2
pF towards local VSS when enabled. The filter is enabled out of reset and can be disabled by setting
OPAxLPFDIS in DACn_OPAxCTRL.
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
728
www.energymicro.com