EFM32WG Datasheet, PDF (150/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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Bit
Name
Reset
Access Description
Used to check the synchronization status of CMU_LFAPRESC0.
Value
0
1
Description
CMU_LFAPRESC0 is ready for update.
CMU_LFAPRESC0 is busy synchronizing new value.
1
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
0
LFACLKEN0
0
R
Low Frequency A Clock Enable 0 Busy
Used to check the synchronization status of CMU_LFACLKEN0.
Value
0
1
Description
CMU_LFACLKEN0 is ready for update.
CMU_LFACLKEN0 is busy synchronizing new value.
11.5.20 CMU_FREEZE - Freeze Register
Offset
0x054
Reset
Access
Bit Position
Name
Bit
31:1
0
Name
Reset
Access Description
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
REGFREEZE
0
RW
Register Update Freeze
When set, the update of the Low Frequency clock control registers is postponed until this bit is cleared. Use this bit to update several
registers simultaneously.
Value
0
1
Mode
UPDATE
FREEZE
Description
Each write access to a Low Frequency clock control register is updated into the Low
Frequency domain as soon as possible.
The LE Clock Control registers are not updated with the new written value.
11.5.21 CMU_LFACLKEN0 - Low Frequency A Clock Enable Register 0
(Async Reg)
Offset
0x058
Reset
Access
Bit Position
Name
Bit
Name
31:4
Reserved
Reset
Access Description
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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