EFM32WG Datasheet, PDF (359/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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Bit
29
28
27
26
25
24
23
22
21
20
19
18
17:15
14
Name
Reset
Access Description
In Host mode, this interrupt is asserted when a session request is detected from the device. In Device mode, this interrupt is asserted
when the VBUS voltage reaches the session-valid level. This bit can be set only by the core and the application should write 1 to clear.
DISCONNINT
0
RW1
Disconnect Detected Interrupt (host only)
Asserted when a device disconnect is detected. This bit can be set only by the core and the application should write 1 to clear it.
CONIDSTSCHNG
1
RW1
Connector ID Status Change (host and device)
The core sets this bit when there is a change in connector ID status. This bit can be set only by the core and the application should
write 1 to clear it.
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
PTXFEMP
1
R
Periodic TxFIFO Empty (host only)
This interrupt is asserted when the Periodic Transmit FIFO is either half or completely empty and there is space for at least one entry
to be written in the Periodic Request Queue. The half or completely empty status is determined by the Periodic TxFIFO Empty Level
bit in the Core AHB Configuration register (USB_GAHBCFG.PTXFEMPLVL).
HCHINT
0
R
Host Channels Interrupt (host only)
The core sets this bit to indicate that an interrupt is pending on one of the channels of the core (in Host mode). The application must
read the Host All Channels Interrupt (USB_HAINT) register to determine the exact number of the channel on which the interrupt
occurred, and then read the corresponding Host Channel-x Interrupt (USB_HCx_INT) register to determine the exact cause of the
interrupt. The application must clear the appropriate status bit in the USB_HCx_INT register to clear this bit.
PRTINT
0
R
Host Port Interrupt (host only)
The core sets this bit to indicate a change in port status in Host mode. The application must read the Host Port Control and Status
(USB_HPRT) register to determine the exact event that caused this interrupt. The application must clear the appropriate status bit
in the Host Port Control and Status register to clear this bit.
RESETDET
0
RW1
Reset detected Interrupt (device only)
In Device mode, this interrupt is asserted when a reset is detected on the USB in EM2 when the device is in Suspend.
In Host mode, this interrupt is not asserted.
FETSUSP
0
RW1
Data Fetch Suspended (device only)
This interrupt is valid only in DMA mode. This interrupt indicates that the core has stopped fetching data for IN endpoints due to the
unavailability of TxFIFO space or Request Queue space. This interrupt is used by the application for an endpoint mismatch algorithm.
For example, after detecting an endpoint mismatch, the application: Sets a Global non-periodic IN NAK handshake, Disables In
endpoints, Flushes the FIFO, Determines the token sequence from the IN Token Sequence, Re-enables the endpoints, Clears the
Global non-periodic IN NAK handshake.
If the Global non-periodic IN NAK is cleared, the core has not yet fetched data for the IN endpoint, and the IN token is received: the
core generates an IN Token Received when FIFO Empty interrupt. The OTG then sends the host a NAK response. To avoid this
scenario, the application can check the USB_GINTSTS.FETSUSP interrupt, which ensures that the FIFO is full before clearing a
Global NAK handshake. Alternatively, the application can mask the IN Token Received when FIFO Empty interrupt when clearing
a Global IN NAK handshake.
INCOMPLP
0
RW1
Incomplete Periodic Transfer (device only)
In Host mode, the core sets this interrupt bit when there are incomplete periodic transactions still pending which are scheduled for the
current frame. In Device mode, the core sets this interrupt to indicate that there is at least one isochronous OUT endpoint on which
the transfer is not completed in the current frame. This bit can be set only by the core and the application should write 1 to clear it.
INCOMPISOIN
0
RW1
Incomplete Isochronous IN Transfer (device only)
The core sets this interrupt to indicate that there is at least one isochronous IN endpoint on which the transfer is not completed in
the current frame.
OEPINT
0
R
OUT Endpoints Interrupt (device only)
The core sets this bit to indicate that an interrupt is pending on one of the OUT endpoints of the core (in Device mode). The application
must read the Device All Endpoints Interrupt (USB_DAINT) register to determine the exact number of the OUT endpoint on which
the interrupt occurred, and then read the corresponding Device OUT Endpoint-x Interrupt (USB_DOEP0INT/USB_DOEPx_INT)
register to determine the exact cause of the interrupt. The application must clear the appropriate status bit in the corresponding
USB_DOEP0INT/USB_DOEPx_INT register to clear this bit.
IEPINT
0
R
IN Endpoints Interrupt (device only)
The core sets this bit to indicate that an interrupt is pending on one of the IN endpoints of the core (in Device mode). The application
must read the Device All Endpoints Interrupt (USB_DAINT) register to determine the exact number of the IN endpoint on Device IN
Endpoint-x Interrupt (USB_DIEP0INT/USB_DIEPx_INT) register to determine the exact cause of the interrupt. The application must
clear the appropriate status bit in the corresponding USB_DIEP0INT/USB_DIEPx_INT register to clear this bit.
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
ISOOUTDROP
0
RW1
Isochronous OUT Packet Dropped Interrupt (device only)
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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