EFM32WG Datasheet, PDF (344/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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Host, the application must not access registers from the other mode. If an illegal access occurs, a Mode
Mismatch interrupt is generated and reflected in the Core Interrupt register (USB_GINTSTS.MODEMIS).
When the core switches from one mode to another, the registers in the new mode must be reprogrammed
as they would be after a power-on reset.
The memory map for the core is as follows:
• Core Global Registers are located in the address offset-range [0x3C000, 0x3C3FF] and typically start
with first letter G.
• Host Mode Registers are located in the address offset-range [0x3C400, 0x3C7FF] and start with first
letter H.
• Device Mode Registers are located in the address offset-range [0x3C800, 0x3CDFF] and start with
first letter D.
• The Power and Clock Gating register is located at offset 0x3CE00.
• The Device EP/Host Channel FIFOs start at address offset 0x3D000 with 4K spacing. These registers,
available in both Host and Device modes, are used to read or write the FIFO space for a specific
endpoint or a channel, in a given direction. If a host channel is of type IN, the FIFO can only be read on
the channel. Similarly, if a host channel is of type OUT, the FIFO can only be written on the channel.
• The Direct RAM Access area start at address offset 0x5C000.
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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