EFM32WG Datasheet, PDF (328/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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Packet Size / 4) + 1 spaces must be allotted to receive back-to-back packets. Typically, two (Largest
Packet Size / 4) + 1 spaces are recommended so that when the previous packet is being transferred
to AHB, the USB can receive the subsequent packet. If AHB latency is high, you must allocate
enough space to receive multiple packets. This is critical to prevent dropping any isochronous
packets.
• Along with each endpoint's last packet, transfer complete status information is also pushed to the
FIFO. Typically, one location for each OUT endpoint is recommended.
2. Transmit FIFO RAM Allocation:
The minimum RAM space required for each IN Endpoint Transmit FIFO is the maximum packet size
for that particular IN endpoint.
More space allocated in the transmit IN Endpoint FIFO results in a better performance on the USB
and can hide latencies on the AHB.
Table 15.3.
FIFO Name
Receive data FIFO
Transmit FIFO 0
Transmit FIFO 1
Transmit FIFO 2
...
Transmit FIFO i
Data RAM Size
rx_fifo_size. This must include RAM for setup packets, OUT
endpoint control information and data OUT packets, as
mentioned earlier.
tx_fifo_size[0]
tx_fifo_size[1]
tx_fifo_size[2]
...
tx_fifo_size[i]
With this information, the following registers must be programmed as follows:
1. Receive FIFO Size Register (USB_GRXFSIZ)
USB_GRXFSIZ.Receive FIFO Depth = rx_fifo_size;
2. Device IN Endpoint Transmit FIFO0 Size Register (USB_GNPTXFSIZ)
USB_GNPTXFSIZ.non-periodic Transmit FIFO Depth = tx_fifo_size[0];
USB_GNPTXFSIZ.non-periodic Transmit RAM Start Address = rx_fifo_size;
3. Device IN Endpoint Transmit FIFO#1 Size Register (USB_DIEPTXF1)
USB_DIEPTXF1. Transmit RAM Start Address = USB_GNPTXFSIZ.FIFO0 Transmit RAM Start
Address + tx_fifo_size[0];
4. Device IN Endpoint Transmit FIFO#2 Size Register (USB_DIEPTXF2)
USB_DIEPTXF2.Transmit RAM Start Address = USB_DIEPTXF1.Transmit RAM Start Address +
tx_fifo_size[1];
5. Device IN Endpoint Transmit FIFO#i Size Register (USB_DIEPTXFi)
USB_DIEPTXFm.Transmit RAM Start Address = USB_DIEPTXFi-1.Transmit RAM Start Address +
tx_fifo_size[i-1];
6. The transmit FIFOs and receive FIFO must be flushed after the RAM allocation is done, for the proper
functioning of the FIFOs.
• USB_GRSTCTL.TXFNUM = 0x10
• USB_GRSTCTL.TXFFLSH = 1
• USB_GRSTCTL.RXFFLSH = 1
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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