EFM32WG Datasheet, PDF (436/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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16.5.3 I2Cn_STATE - State Register
Offset
0x008
Reset
Access
Bit Position
Name
Bit
31:8
7:5
4
3
2
1
0
Name
Reset
Access Description
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
STATE
0x0
R
Transmission State
The state of any current transmission. Cleared if the I²C module is idle.
Value
0
1
2
3
4
5
6
Mode
IDLE
WAIT
START
ADDR
ADDRACK
DATA
DATAACK
Description
No transmission is being performed.
Waiting for idle. Will send a start condition as soon as the bus is idle.
Start transmitted or received
Address transmitted or received
Address ack/nack transmitted or received
Data transmitted or received
Data ack/nack transmitted or received
BUSHOLD
0
R
Set if the bus is currently being held by this I²C module.
Bus Held
NACKED
0
R
Nack Received
Set if a NACK was received and STATE is ADDRACK or DATAACK.
TRANSMITTER
0
R
Transmitter
Set when operating as a master transmitter or a slave transmitter. When cleared, the system may be operating as a master receiver,
a slave receiver or the current mode is not known.
MASTER
0
R
Master
Set when operating as an I²C master. When cleared, the system may be operating as an I²C slave.
BUSY
1
R
Bus Busy
Set when the bus is busy. Whether the I²C module is in control of the bus or not has no effect on the value of this bit. When the
MCU comes out of reset, the state of the bus is not known, and thus BUSY is set. Use the ABORT command or a bus idle timeout
to force the I²C module out of the BUSY state.
16.5.4 I2Cn_STATUS - Status Register
Offset
0x00C
Reset
Access
Bit Position
Name
Bit
Name
31:9
Reserved
Reset
Access Description
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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