EFM32WG Datasheet, PDF (265/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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must read the NAK/ACK along with the xact_err. If NAK/ACK is not set, the Xact_err count must be
incremented otherwise application must initialize the Xact_err count to 1.
Bulk/Control OUT/SETUP
Unmask (CHHLTD)
if (CHHLTD)
{
if (XFERCOMPL or STALL)
{
Reset Error Count (Error_count=1)
Mask ACK
De-allocate Channel
}
else if (XACTERR)
{
if (NAK/ACK)
{
Error_count = 1
Re-initialize Channel
Rewind Buffer Pointers
}
else
{
Error_count = Error_count + 1
if (Error_count == 3)
{
De allocate channel
}
else
{
Re-initialize Channel
Rewind Buffer Pointers
}
}
}
}
else if (ACK)
{
Reset Error Count (Error_count=1)
Mask ACK
}
As soon as the channel is enabled, the core attempts to fetch and write data packets, in multiples of
the maximum packet size, to the transmit FIFO when space is available in the transmit FIFO and the
Request queue. The core stops fetching as soon as the last packet is fetched.
15.4.3.6.8 Bulk and Control IN Transactions in DMA Mode
To initialize the core after power-on reset, the application must follow the sequence in Overview:
Programming the Core (p. 246) . Before it can communicate with the connected device, it must initialize
a channel as described in Channel Initialization (p. 252) .
A typical bulk or control IN operation in DMA mode is shown in Figure 15.13 (p. 263) . See channel
2 (ch_2).
The assumptions are:
1. The application is attempting to receive two maximum-packet-size packets (transfer size = 1,024
bytes).
2. The receive FIFO can hold at least one maximum-packet-size packet and two status DWORDs per
packet (72 bytes for FS).
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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