EFM32WG Datasheet, PDF (34/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

...the world's most energy friendly microcontrollers
There are 32 page lock bits per page lock word (PLW). Bit 0 refers to the first page and bit 31 refers
to the last page within a PLW. Thus, PLW[0] contains lock bits for page 0-31 in the main block, PLW[1]
contains lock bits for page 32-63 etc. A page is locked when the bit is 0. A locked page cannot be erased
or written.
Word 127 is the debug lock word (DLW). The four LSBs of this word are the debug lock bits. If these bits
are 0xF, then debug access is enabled. Debug access to the core is disabled from power-on reset until
the DLW is evaluated immediately before the Cortex-M4 starts execution of the user application code.
If the bits are not 0xF, then debug access to the core remains blocked.
Word 126 is the user page lock word (ULW). Bit 0 of this word is the User Data Page lock bit. Bit 1 in
this word locks the Lock Bits Page. The lock bits can be reset by a device erase operation initiated from
the Authentication Access Port (AAP) registers. The AAP is described in more detail in Section 6.4 (p.
27) . Note that the AAP is only accessible from the debug interface, and cannot be accessed from the
Cortex-M4 core.
Word 125 is the mass erase lock word (MLW). Bit 0 locks the entire flash. The mass erase lock bits will
not have any effect on device erases initiated from the Authentication Access Port (AAP) registers. The
AAP is described in more detail in Section 6.4 (p. 27) .
7.3.3 Device Information (DI) Page
This read-only page holds oscillator, DAC and ADC calibration data from the production test as well as
an unique device ID. The page is further described in Section 5.6 (p. 24) .
7.3.4 Device Revision
The device revision number is read from the ROM Table. The major revision number and the chip family
number is read from PID0 and PID1 registers. The minor revision number is extracted from the PID2 and
PID3 registers, as illustrated in Figure 7.1 (p. 34) . The Fam[5:2] and Fam[1:0] must be combined
to complete the chip family number, while the Minor Rev[7:4] and Minor Rev[3:0] must be combined to
form the complete revision number.
Figure 7.1. Revision Number Extraction
PID2 (0 xE0 0 FFFE8 )
31:8
7:4
3:0
Minor Rev[ 7:4]
PID0 (0 xE0 0 FFFE0 )
31:7 6:5
5:0
Fam [ 1:0] Major Rev[ 5:0]
PID3 (0 xE0 0 FFFEC)
31:8
7:4
3:0
Minor Rev[ 3:0]
PID1 (0 xE0 0 FFFE4 )
31:4
3:0
Fam [ 5:2]
For the Wonder Gecko family, the chip family number is 0x3 and the major revision number is 0x1. The
minor revision number is to be interpreted according to Table 7.3 (p. 34) .
Table 7.3. Revision Number Interpretation
Revision[7:0]
0x00
Revision
A
7.3.5 Post-reset Behavior
Calibration values are automatically written to registers by the MSC before application code startup. The
values are also available to read from the DI page for later reference by software. Other information
such as the device ID and production date is also stored in the DI page and is readable from software.
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
34
www.energymicro.com