EFM32WG Datasheet, PDF (400/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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Bit
Name
Reset
Access Description
13
NAKINTRPT
0
RW1
NAK Interrupt
The core generates this interrupt when a NAK is transmitted or received by the device.
12
BBLEERR
0
RW1
Babble Error
The core generates this interrupt when babble is received for the endpoint.
11
PKTDRPSTS
0
RW1
Packet Drop Status
This bit indicates to the application that an ISO OUT packet has been dropped. This bit does not have an associated mask bit and
does not generate an interrupt.
10:7
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
6
BACK2BACKSETUP
0
RW1
Back-to-Back SETUP Packets Received
Applies to Control OUT endpoints only. This bit indicates that the core has received more than three back-to-back SETUP packets
for this particular endpoint.
5
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
4
OUTTKNEPDIS
0
RW1
OUT Token Received When Endpoint Disabled
Applies only to control OUT endpoints. Indicates that an OUT token was received when the endpoint was not yet enabled. This
interrupt is asserted on the endpoint for which the OUT token was received.
3
SETUP
0
RW1
Setup Phase Done
Applies to control OUT endpoints only. Indicates that the SETUP phase for the control endpoint is complete and no more back-
to-back SETUP packets were received for the current control transfer. On this interrupt, the application can decode the received
SETUP data packet.
2
AHBERR
0
RW1
AHB Error
This is generated only in DMA mode when there is an AHB error during an AHB read/write. The application can read the corresponding
endpoint DMA address register to get the error address.
1
EPDISBLD
0
RW1
Endpoint Disabled Interrupt
This bit indicates that the endpoint is disabled per the application's request.
0
XFERCOMPL
0
RW1
Transfer Completed Interrupt
This field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint.
15.6.66 USB_DOEPx_TSIZ - Device OUT Endpoint x+1 Transfer Size
Register
The application must modify this register before enabling the endpoint. Once the endpoint is enabled
using Endpoint Enable bit of the Device Endpoint x+1 Control register (USB_DOEPx_CTL.EPENA), the
core modifies this register. The application can only read this register once the core has cleared the
Endpoint Enable bit.
Offset
0x3CB30
Bit Position
Reset
Access
Name
Bit
Name
31
Reserved
Reset
Access Description
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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