EFM32WG Datasheet, PDF (712/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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29.5.2 DACn_STATUS - Status Register
Offset
0x004
Reset
Access
Bit Position
Name
Bit
Name
Reset
Access Description
31:2
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
1
CH1DV
0
R
Channel 1 Data Valid
This bit is set high when CH1DATA is written and is set low when CH1DATA is used in conversion.
0
CH0DV
0
R
Channel 0 Data Valid
This bit is set high when CH0DATA is written and is set low when CH0DATA is used in conversion.
29.5.3 DACn_CH0CTRL - Channel 0 Control Register
Offset
0x008
Reset
Access
Bit Position
Name
Bit
31:8
7:4
3
2
Name
Reset
Access Description
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
PRSSEL
0x0
RW
Channel 0 PRS Trigger Select
Select Channel 0 PRS input channel.
Value
0
1
2
3
4
5
6
7
8
9
10
11
Mode
PRSCH0
PRSCH1
PRSCH2
PRSCH3
PRSCH4
PRSCH5
PRSCH6
PRSCH7
PRSCH8
PRSCH9
PRSCH10
PRSCH11
Description
PRS ch 0 triggers channel 0 conversion.
PRS ch 1 triggers channel 1 conversion.
PRS ch 2 triggers channel 2 conversion.
PRS ch 3 triggers channel 3 conversion.
PRS ch 4 triggers channel 4 conversion.
PRS ch 5 triggers channel 5 conversion.
PRS ch 6 triggers channel 6 conversion.
PRS ch 7 triggers channel 7 conversion.
PRS ch 8 triggers channel 8 conversion.
PRS ch 9 triggers channel 9 conversion.
PRS ch 10 triggers channel 10 conversion.
PRS ch 11 triggers channel 11 conversion.
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
PRSEN
0
Select Channel 0 conversion trigger.
RW
Channel 0 PRS Trigger Enable
Value
0
Description
Channel 0 is triggered by CH0DATA or COMBDATA write
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
712
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