EFM32WG Datasheet, PDF (158/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

12.3.1 Clock Source
...the world's most energy friendly microcontrollers
Three clock sources are available for use with the watchdog, through the CLKSEL field in WDOG_CTRL.
The corresponding clocks must be enabled in the CMU. The SWOSCBLOCK bit in WDOG_CTRL can be
written to prevent accidental disabling of the selected clocks. Also, setting this bit will automatically start
the selected oscillator source when the watchdog is enabled. The PERSEL field in WDOG_CTRL is used
to divide the selected watchdog clock, and the timeout for the watchdog timer can be calculated like this:
WDOG Timeout Equation
T_TIMEOUT = (2^3+PERSEL + 1)/f,
(12.1)
where f is the frequency of the selected clock.
It is recommended to clear the watchdog first, if PERSEL is changed while the watchdog is enabled.
To use this module, the LE interface clock must be enabled in CMU_HFCORECLKEN0, in addition to
the module clock.
12.3.2 Debug Functionality
The watchdog timer can either keep running or be frozen when the device is halted by a debugger. This
configuration is done through the DEBUGRUN bit in WDOG_CTRL. When code execution is resumed,
the watchdog will continue counting where it left off.
12.3.3 Energy Mode Handling
The watchdog timer can be configured to either keep on running or freeze when entering EM2 or EM3.
The configuration is done individually for each energy mode in the EM2RUN and EM3RUN bits in
WDOG_CTRL. When the watchdog has been frozen and is re-entering an energy mode where it is
running, the watchdog timer will continue counting where it left off. For the watchdog there is no difference
between EM0 and EM1. The watchdog does not run in EM4, and if EM4BLOCK in WDOG_CTRL is set,
the CPU is prevented from entering EM4.
Note
If the WDOG is clocked by the LFXO or LFRCO, writing the SWOSCBLOCK bit will
effectively prevent the CPU from entering EM3. When running from the ULFRCO, writing
the SWOSCBLOCK bit will prevent the CPU from entering EM4.
12.3.4 Register access
Since this module is a Low Energy Peripheral, and runs off a clock which is asynchronous to
the HFCORECLK, special considerations must be taken when accessing registers. Please refer to
Section 5.3 (p. 21) for a description on how to perform register accesses to Low Energy Peripherals.
note that clearing the EN bit in WDOG_CTRL will reset the WDOG module, which will halt any ongoing
register synchronization.
Note
Never write to the WDOG registers when it is disabled, except to enable by setting the EN
bitfield in WDOG_CTRL.
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
158
www.energymicro.com