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Task C
Primary, copy D
Task D
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8. The controller generates an auto-request for the channel and then arbitrates.
9. The controller performs task C. After it completes the task, it generates an
auto-request for the channel and then arbitrates.
10.The controller performs four DMA transfers. These transfers write the alternate
data structure for task D.
11.The controller sets the cycle_ctrl bits of the primary data structure to b000, to
indicate that this data structure is now invalid.
12.The controller generates an auto-request for the channel and then arbitrates.
13.The controller performs task D using an auto-request cycle.
14.The controller sets dma_done[C] HIGH for one HFCORECLK cycle and enters
the arbitration process.
8.4.2.3.6 Peripheral scatter-gather
In peripheral scatter-gather mode the controller receives an initial request from a peripheral and then it
performs four DMA transfers using the primary data structure. It then immediately starts a DMA cycle
using the alternate data structure, without re-arbitrating.
Note
These are the only circumstances, where the controller does not enter the arbitration
process after completing a transfer using the primary data structure.
After this cycle completes, the controller re-arbitrates and if the controller receives a request from the
peripheral that has the highest priority then it performs another four DMA transfers using the primary
data structure. It then immediately starts a DMA cycle using the alternate data structure, without re-
arbitrating. The controller continues to switch from primary to alternate to primary… until either:
• the host processor configures the alternate data structure for a basic cycle
• it reads an invalid data structure.
Note
After the controller completes the N primary transfers it invalidates the primary data
structure by setting the cycle_ctrl field to b000.
The controller asserts dma_done[C] when the scatter-gather transaction completes using a basic cycle.
In scatter-gather mode, the controller uses the primary data structure to program the alternate data
structure. Table 8.5 (p. 60) lists the fields of the channel_cfg memory location for the primary data
structure, that you must program with constant values and those that can be user defined.
Table 8.5. channel_cfg for a primary data structure, in peripheral scatter-gather mode
Bit
Field
Constant-value fields:
[31:30] dst_inc
[29:28] dst_size
[27:26] src_inc
[25:24] src_size
[17:14] R_power
[2:0]
cycle_ctrl
User defined values:
[23:21] dst_prot_ctrl
[20:18] src_prot_ctrl
Value Description
b10
Configures the controller to use word increments for the address
b10
Configures the controller to use word transfers
b10
Configures the controller to use word increments for the address
b10
Configures the controller to use word transfers
b0010 Configures the controller to perform four DMA transfers
b110 Configures the controller to perform a peripheral scatter-gather DMA cycle
-
Configures the state of HPROT when the controller writes the destination data
-
Configures the state of HPROT when the controller reads the source data
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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