EFM32WG Datasheet, PDF (55/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

...the world's most energy friendly microcontrollers
DMA transfer completes. Therefore, you must take care when setting the R_power, that you do not
significantly increase the latency for high-priority channels.
8.4.2.3.1 Invalid
After the controller completes a DMA cycle it sets the cycle type to invalid, to prevent it from repeating
the same DMA cycle.
8.4.2.3.2 Basic
In this mode, you configure the controller to use either the primary or the alternate data structure. After
you enable the channel C and the controller receives a request for this channel, then the flow for this
DMA cycle is as follows:
1. The controller performs 2^R transfers. If the number of transfers remaining becomes zero, then the
flow continues at step 3 (p. 55) .
2. The controller arbitrates:
• if a higher-priority channel is requesting service then the controller services that channel
• if the peripheral or software signals a request to the controller then it continues at step 1 (p. 55) .
3. The controller sets dma_done[C] HIGH for one HFCORECLK cycle. This indicates to the host
processor that the DMA cycle is complete.
8.4.2.3.3 Auto-request
When the controller operates in this mode, it is only necessary for it to receive a single request to enable
it to complete the entire DMA cycle. This enables a large data transfer to occur, without significantly
increasing the latency for servicing higher priority requests, or requiring multiple requests from the
processor or peripheral.
You can configure the controller to use either the primary or the alternate data structure. After you enable
the channel C and the controller receives a request for this channel, then the flow for this DMA cycle
is as follows:
1. The controller performs 2^R transfers for channel C. If the number of transfers remaining is zero the
flow continues at step 3 (p. 55) .
2. The controller arbitrates. When channel C has the highest priority then the DMA cycle continues at
step 1 (p. 55) .
3. The controller sets dma_done[C] HIGH for one HFCORECLK cycle. This indicates to the host
processor that the DMA cycle is complete.
8.4.2.3.4 Ping-pong
In ping-pong mode, the controller performs a DMA cycle using one of the data structures (primary or
alternate) and it then performs a DMA cycle using the other data structure. The controller continues to
switch from primary to alternate to primary… until it reads a data structure that is invalid, or until the
host processor disables the channel.
Figure 8.3 (p. 56) shows an example of a ping-pong DMA transaction.
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
55
www.energymicro.com