EFM32WG Datasheet, PDF (36/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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7.3.5.6 Instruction Cache
The MSC includes an instruction cache. The instruction cache for the internal flash memory is enabled
by default, but can be disabled by setting IFCDIS in MSC_READCTRL. When enabled, the instruction
cache typically reduces the number of flash reads significantly, thus saving energy. In most cases a
cache hit-rate of more than 70 % is achievable. When a 32-bit instruction fetch hits in the cache the data
is returned to the processor in one clock cycle. Thus, performance is also improved when wait-states
are used (i.e. running at frequencies above 16 MHz).
The instruction cache is connected directly to the ICODE bus on the Cortex-M4 and functions as a
memory access filter between the processor and the memory system, as illustrated in Figure 7.2 (p.
36) . The cache consists of an access filter, lookup logic, a 128x32 SRAM (512 bytes) and two
performance counters. The access filter checks that the address for the access is to on-chip flash
memory (instructions in RAM are not cached). If the address matches, the cache lookup logic and SRAM
is enabled. Otherwise, the cache is bypassed and the access is forwarded to the memory system.
The cache is then updated when the memory access completes. The access filter also disables cache
updates for interrupt context accesses if caching in interrupt context is disabled. The performance
counters, when enabled, keep track of the number of cache hits and misses. The cache consists of 16
8-word cachelines organized as 4 sets with 4 ways. The cachelines are filled up continuously one word
at a time as the individual words are requested by the processor. Thus, not all words of a cacheline
might be valid at a given time.
Figure 7.2. Instruction Cache
CODE
Mem ory Space
Inst ruct ion Cache
ICODE
AHB-Lit e Bus
IDCODE
AHB-Lit e Bus
IDCODE
MUX
Ca c h e
Look-up Logic
128x32
SRAM
Access
Filt er
Perform ance Count ers
ICODE
AHB-Lit e Bus
Cort ex
DCODE
AHB-Lit e Bus
By default, the instruction cache is automatically invalidated when the contents of the flash is changed
(i.e. written or erased). In many cases, however, the application only makes changes to data in the
flash, not code. In this case, the automatic invalidate feature can be disabled by setting AIDIS in
MSC_READCTRL. The cache can (independent of the AIDIS setting) be manually invalidated by writing
1 to INVCACHE in MSC_CMD.
In general it is highly recommended to keep the cache enabled all the time. However, for some sections
of code with very low cache hit-rate more energy-efficient execution can be achieved by disabling the
cache temporarily. To measure the hit-rate of a code-section, the built-in performance counters can
be used. Before the section, start the performance counters by writing 1 to STARTPC in MSC_CMD.
This starts the performance counters, counting from 0. At the end of the section, stop the performance
counters by writing 1 to STOPPC in MSC_CMD. The number of cache hits and cache misses for
that section can then be read from MSC_CACHEHITS and MSC_CACHEMISSES respectively. The
total number of 32-bit instruction fetches will be MSC_CACHEHITS + MSC_CACHEMISSES. Thus, the
cache hit-ratio can be calculated as MSC_CACHEHITS / (MSC_CACHEHITS + MSC_CACHEMISSES).
When MSC_CACHEHITS overflows the CHOF interrupt flag is set. When MSC_CACHEMISSES
overflows the CMOF interrupt flag is set. These flags must be cleared explicitly by software. The
range of the performance counters can thus be extended by increasing a counter in the MSC interrupt
routine. The performance counters only count when a cache lookup is performed. If the lookup fails,
MSC_CACHEMISSES is increased. If the lookup is successful, MSC_CACHEHITS is increased. For
example, a cache lookup is not performed if the cache is disabled or the code is executed from
RAM. When caching of vector fetches and instructions in interrupt routines is disabled (ICCDIS in
MSC_READCTRL is set), the performance counters do not count when these types of fetches occur
(i.e. while in interrupt context).
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