EFM32WG Datasheet, PDF (87/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

...the world's most energy friendly microcontrollers
Bit
Name
Reset
Access Description
5
CH5REQSTATUS
0
R
Channel 5 Request Status
When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to service
the DMA channel. The controller services the request by performing the DMA cycle using 2^R DMA transfers.
4
CH4REQSTATUS
0
R
Channel 4 Request Status
When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to service
the DMA channel. The controller services the request by performing the DMA cycle using 2^R DMA transfers.
3
CH3REQSTATUS
0
R
Channel 3 Request Status
When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to service
the DMA channel. The controller services the request by performing the DMA cycle using 2^R DMA transfers.
2
CH2REQSTATUS
0
R
Channel 2 Request Status
When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to service
the DMA channel. The controller services the request by performing the DMA cycle using 2^R DMA transfers.
1
CH1REQSTATUS
0
R
Channel 1 Request Status
When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to service
the DMA channel. The controller services the request by performing the DMA cycle using 2^R DMA transfers.
0
CH0REQSTATUS
0
R
Channel 0 Request Status
When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to service
the DMA channel. The controller services the request by performing the DMA cycle using 2^R DMA transfers.
8.7.19 DMA_CHSREQSTATUS - Channel Single Request Status
Offset
0xE18
Reset
Access
Bit Position
Name
Bit
31:12
11
10
9
8
7
6
Name
Reset
Access Description
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
CH11SREQSTATUS
0
R
Channel 11 Single Request Status
When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to service
the DMA channel. The controller services the request by performing the DMA cycle using single DMA transfers.
CH10SREQSTATUS
0
R
Channel 10 Single Request Status
When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to service
the DMA channel. The controller services the request by performing the DMA cycle using single DMA transfers.
CH9SREQSTATUS
0
R
Channel 9 Single Request Status
When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to service
the DMA channel. The controller services the request by performing the DMA cycle using single DMA transfers.
CH8SREQSTATUS
0
R
Channel 8 Single Request Status
When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to service
the DMA channel. The controller services the request by performing the DMA cycle using single DMA transfers.
CH7SREQSTATUS
0
R
Channel 7 Single Request Status
When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to service
the DMA channel. The controller services the request by performing the DMA cycle using single DMA transfers.
CH6SREQSTATUS
0
R
Channel 6 Single Request Status
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
87
www.energymicro.com