EFM32WG Datasheet, PDF (599/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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Bit
Name
Reset
Access Description
2
UF
0
RW
Underflow Interrupt Enable
Set to enable interrupt on the UF interrupt flag.
1
COMP1
0
RW
Compare Match 1 Interrupt Enable
Set to enable interrupt on the COMP1 interrupt flag.
0
COMP0
0
RW
Compare Match 0 Interrupt Enable
Set to enable interrupt on the COMP0 interrupt flag.
23.5.13 LETIMERn_FREEZE - Freeze Register
Offset
0x030
Reset
Access
Bit Position
Name
Bit
31:1
0
Name
Reset
Access Description
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
REGFREEZE
0
RW
Register Update Freeze
With the immediate write synchronization scheme the REGFREEZE register is no longer used.
Value
0
1
Mode
UPDATE
FREEZE
Description
Each write access to a LETIMER register is updated into the Low Frequency domain
as soon as possible.
The LETIMER is not updated with the new written value.
23.5.14 LETIMERn_SYNCBUSY - Synchronization Busy Register
Offset
0x034
Reset
Access
Bit Position
Name
Bit
Name
Reset
Access Description
31:6
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
5
REP1
0
R
REP1 Register Busy
Set when the value written to REP1 is being synchronized.
4
REP0
0
R
REP0 Register Busy
Set when the value written to REP0 is being synchronized.
3
COMP1
0
R
COMP1 Register Busy
Set when the value written to COMP1 is being synchronized.
2
COMP0
0
R
COMP0 Register Busy
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
599
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