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25.5.15 LESENSE_IDLECONF - GPIO Idle phase configuration (Async Reg)
For more information about Asynchronous Registers please see Section 5.3 (p. 21) .
Offset
Bit Position
0x038
Reset
Access
Name
Bit
31:30
Name
CH15
Reset
0x0
Access
RW
Description
Channel 15 idle phase configuration
29:28
Value
0
1
2
3
CH14
Mode
DISABLE
HIGH
LOW
DACCH1
0x0
Description
CH15 output is disabled in idle phase
CH15 output is high in idle phase
CH15 output is low in idle phase
CH15 output is connected to DAC CH1 output in idle phase
RW
Channel 14 idle phase configuration
27:26
Value
0
1
2
3
CH13
Mode
DISABLE
HIGH
LOW
DACCH1
0x0
Description
CH14 output is disabled in idle phase
CH14 output is high in idle phase
CH14 output is low in idle phase
CH14 output is connected to DAC CH1 output in idle phase
RW
Channel 13 idle phase configuration
25:24
Value
0
1
2
3
CH12
Mode
DISABLE
HIGH
LOW
DACCH1
0x0
Description
CH13 output is disabled in idle phase
CH13 output is high in idle phase
CH13 output is low in idle phase
CH13 output is connected to DAC CH1 output in idle phase
RW
Channel 12 idle phase configuration
23:22
Value
0
1
2
3
CH11
Mode
DISABLE
HIGH
LOW
DACCH1
0x0
Description
CH12 output is disabled in idle phase
CH12 output is high in idle phase
CH12 output is low in idle phase
CH12 output is connected to DAC CH1 output in idle phase
RW
Channel 11 idle phase configuration
21:20
Value
0
1
2
CH10
Mode
DISABLE
HIGH
LOW
0x0
Description
CH11 output is disabled in idle phase
CH11 output is high in idle phase
CH11 output is low in idle phase
RW
Channel 10 idle phase configuration
Value
0
1
Mode
DISABLE
HIGH
Description
CH10 output is disabled in idle phase
CH10 output is high in idle phase
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
643
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