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EFM32WG Datasheet, PDF (278/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.
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{
Reset Error Count
De-allocate Channel
}
else
{
Unmask CHHLTD
Disable Channel
}
}
else if (XACTERR or BBLERR)
{
Increment Error Count
Unmask CHHLTD
Disable Channel
}
else if (CHHLTD)
{
Mask CHHLTD
if (Transfer Done or (Error_count == 3))
{
De-allocate Channel
}
else
{
Re-initialize Channel
}
}
15.4.3.6.15 Isochronous OUT Transactions in DMA Mode
To initialize the core after power-on reset, the application must follow the sequence in Overview:
Programming the Core (p. 246) . Before it can communicate with the connected device, it must initialize
a channel as described in Channel Initialization (p. 252) .
A typical isochronous OUT operation in DMA mode is shown in Figure 15.18 (p. 279) . See channel
1 (ch_1). The assumptions are:
• The application is attempting to transmit one packet every frame (up to 1 maximum packet size of
1,024 bytes).
• The Periodic Transmit FIFO can hold one packet (1 KB).
• Periodic Request Queue depth = 4.
15.4.3.6.15.1 Normal Isochronous OUT Operation
1. Initialize and enable channel 1 as explained in Channel Initialization (p. 252) .
2. The host starts fetching the first packet as soon as the channel is enabled, and writes the OUT request
along with the last DWORD fetch. In high-bandwidth transfers, the host continues fetching the next
packet (up to the value specified in the MC field) before switching to the next channel.
3. The host attempts to send an OUT token in the beginning of the next (odd) frame.
4. After successfully transmitting the packet, the host generates a CHHLTD interrupt.
5. In response to the CHHLTD interrupt, reinitialize the channel for the next transfer.
15.4.3.6.15.2 Handling Interrupts
The channel-specific interrupt service routine for Isochronous OUT transactions in DMA mode is shown
in the following flow:
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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