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low for one bit-period. This signals the start of a frame, and is used for synchronization. Following the
start bit are 8 or 9 data bits and an optional parity bit. The data is transmitted with the least significant
bit first. Finally, a number of stop-bits, where the line is driven high, end the frame. The frame format
is shown in Figure 19.2 (p. 495) .
Figure 19.2. LEUART Asynchronous Frame Format
St op or idle
S
0
1
2
3
Fram e
4
5
6
7
[ 8] ^{[ P]}
St op
St art or idle
The number of data bits in a frame is set by DATABITS in LEUARTn_CTRL, and the number of stop-bits
is set by STOPBITS in LEUARTn_CTRL. Whether or not a parity bit should be included, and whether
it should be even or odd is defined by PARITY in LEUARTn_CTRL. For communication to be possible,
all parties of an asynchronous transfer must agree on the frame format being used.
The frame format used by the LEUART can be inverted by setting INV in LEUARTn_CTRL. This affects
the entire frame, resulting in a low idle state, a high start-bit, inverted data and parity bits, and low stop-
bits. INV should only be changed while the receiver is disabled.
19.3.1.1 Parity Bit Calculation and Handling
Hardware automatically inserts parity bits into outgoing frames and checks the parity bits of incoming
frames. The possible parity modes are defined in Table 19.1 (p. 495) . When even parity is chosen,
a parity bit is inserted to make the number of high bits (data + parity) even. If odd parity is chosen, the
parity bit makes the total number of high bits odd. When parity bits are disabled, which is the default
configuration, the parity bit is omitted.
Table 19.1. LEUART Parity Bit
PARITY [1:0]
00
01
10
11
No parity (default)
Reserved
Even parity
Odd parity
Description
See Section 19.3.5.4 (p. 500) for more information on parity bit handling.
19.3.2 Clock Source
The LEUART clock source is selected by the LFB bit field the CMU_LFCLKSEL register. The clock is
prescaled by the LEUARTn bitfield in the CMU_LFBPRESC0 register and enabled by the LEUARTn bit
in the CMU_LFBCLKEN0.
To use this module, the LE interface clock must be enabled in CMU_HFCORECLKEN0, in addition to
the module clock.
19.3.3 Clock Generation
The LEUART clock defines the transmission and reception data rate. The clock generator employs a
fractional clock divider to allow baud rates that are not attainable by integral division of the 32.768 kHz
clock that drives the LEUART.
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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