EFM32WG Datasheet, PDF (755/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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rising and falling edges. By setting the EXT[n] bit in GPIO_IEN, a high interrupt flag n, will trigger one
of two interrupt lines. The even interrupt line is triggered by any enabled even numbered interrupt flag,
while the odd is triggered by odd flags. The interrupt flags can be set and cleared by software by writing
the GPIO_IFS and GPIO_IFC registers, see Example 32.1 (p. 755) . Since the external interrupts
are asynchronous, they are sensitive to noise. To increase noise tolerance, the MODEL and MODEH
fields in the GPIO_Px_MODEL and GPIO_Px_MODEH registers, respectively, should be set to include
filtering for pins that have external interrupts enabled.
Example 32.1. Interrupt Example
Setting EXTIPSEL3 in GPIO_EXTIPSELL to 2 (Port C) and setting the GPIO_EXTIRISE[3] bit, the
interrupt flag EXT[3] in GPIO_IF will be triggered by a rising edge on pin 3 on PORT C. If EXT[3] in
GPIO_IEN is set as well, a interrupt request will be sent on IRQ_GPIO_ODD.
32.3.6 Output to PRS
All pins with the same pin number (n) are grouped together to form one PRS producer output, giving
a total of 16 outputs to the PRS. The port on which the output n should be taken is selected by the
EXTIPSELn[3:0] bits in the GPIO_EXTIPSELL or the GPIO_EXTIPSELH registers.
32.3.7 Synchronization
To avoid metastability in synchronous logic connected to the pins, all inputs are synchronized with
double flip-flops. The flip-flops for the input data run on the HFCORECLK. Consequently, when a
pin changes state, the change will have propagated to GPIO_Px_DIN after 2 positive HFCORECLK
edges, or maximum 2 HFCORECLK cycles. Synchronization (also running on the HFCORECLK) is also
added for interrupt input. The input to the PRS generation is also synchronized, but these flip-flops
run on the HFPERCLK. To save power when the external interrupts or PRS generation is not used,
the synchronization flip-flops for these can be turned off by clearing the INTSENSE or PRSSENSE,
respectively, in GPIO_INSENSE register.
Note
To use the GPIO, the GPIO clock must first be enabled in CMU_HFPERCLKEN0. Setting
this bit enables the HFCORECLK and the HFPERCLK for the GPIO. HFCORECLK is used
for updating registers, while HFPERCLK is only used to synchronize PRS and interrupts.
The PRS and interrupt synchronization can also be disabled through GPIO_INSENSE, if
these are not used.
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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