EFM32WG Datasheet, PDF (23/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

...the world's most energy friendly microcontrollers
peripheral write access. If a write is set up close to a peripheral clock edge, the write is delayed to after
the clock edge. This will introduce wait-states on peripheral access.
For peripherals with delayed synchronization, the SYNCBUSY registers are still present and serve two
purposes: (1) commands written to a peripheral with immediate synchronization are not executed before
the first peripheral clock after the write. During this period, the SYNCBUSY flag in the command register
is set, indicating that the command has not yet been executed; (2) to maintain backwards compatibility
with the EFM32G series, SYNCBUSY registers are also present for other registers. These are however,
always 0, indicating that register writes are always safe.
Note
If the application must be compatible with the EFM32G series, all Low Energy Peripherals
should be accessed as if they only had delayed synchronization, i.e. using SYNCBUSY.
5.3.1.2 Reading
When reading from Low Energy Peripherals, the data is synchronized regardless of the originating clock
domain. Registers updated/maintained by the Low Energy Peripheral are read directly from the Low
Energy clock domain. Registers residing in the core clock domain, are read from the core clock domain.
See Figure 5.4 (p. 23) for a more detailed overview of the read operation.
Note
Writing a register and then immediately reading back the value of the register may give the
impression that the write operation is complete. This is not necessarily the case. Please
refer to the SYNCBUSY register for correct status of the write operation to the Low Energy
Peripheral.
Figure 5.4. Read operation from Low Energy Peripherals
Core Clock Dom ain
Core Clock
Fr e e ze
Regist er 0
Regist er 1
.
.
.
Regist er n
Low Frequency Clock Dom ain
Low Frequency Clock
Synchronizer 0
Synchronizer 1
.
.
.
Synchronizer n
Low Frequency Clock
Regist er 0 Sync
Regist er 1 Sync
.
.
.
Regist er n Sync
Read
Sy n c h r o n i ze r
Read Dat a
HW St at us Regist er 0
HW St at us Regist er 1
.
.
.
HW St at us Regist er m
Low Energy
Pe r i p h e r a l
Main
Funct ion
5.3.2 FREEZE register
For Low Energy Peripherals with delayed synchronization there is a <module_name>_FREEZE register
(e.g. RTC_FREEZE), containing a bit named REGFREEZE. If precise control of the synchronization
process is required, this bit may be utilized. When REGFREEZE is set, the synchronization process is
halted, allowing the software to write multiple Low Energy registers before starting the synchronization
process, thus providing precise control of the module update process. The synchronization process is
started by clearing the REGFREEZE bit.
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
23
www.energymicro.com