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EFM32WG Datasheet, PDF (166/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.
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Module
Reflex Input
Decoder Bit 0
Decoder Bit 1
Decoder Bit 2
Decoder Bit 3
Input Format
Level
Level
Level
Level
Async Support
Yes
Yes
Yes
Yes
Note
It is possible to output prs channel 0 - channel 3 onto the GPIO by setting CH0PEN,
CH1PEN, CH2PEN, or CH3PEN in the PRS_ROUTE register.
13.3.5 Example
The example below (illustrated in Figure 13.2 (p. 166) ) shows how to set up ADC0 to start single
conversions every time TIMER0 overflows (one HFPERCLK cycle high pulse), using PRS channel 5:
• Set SOURCESEL in PRS_CH5_CTRL to 0b011100 to select TIMER0 as input to PRS channel 5.
• Set SIGSEL in PRS_CH5_CTRL to 0b001 to select the overflow signal (from TIMER0).
• Configure ADC0 with the desired conversion set-up.
• Set SINGLEPRSEN in ADC0_SINGLECTRL to 1 to enable single conversions to be started by a high
PRS input signal.
• Set SINGLEPRSSEL in ADC0_SINGLECTRL to 0x5 to select PRS channel 5 as input to start the
single conversion.
• Start TIMER0 with the desired TOP value, an overflow PRS signal is output automatically on overflow.
Note that the ADC results needs to be fetched either by the CPU or DMA.
Figure 13.2. TIMER0 overflow starting ADC0 single conversions through PRS channel 5.
TIMER0
Ov e r f l o w
ADC0
St art single conv.
ch0
ch1
ch2
PRS
ch3
ch4
ch5
ch6
ch7
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
166
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