EFM32WG Datasheet, PDF (184/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

...the world's most energy friendly microcontrollers
A RDHOLDX cycle will automatically get inserted for the following case:
• Between a read and a subsequent write on the EBI_AD lines. Note that this is only possible if NOIDLE/
NOIDLEn is set to 1. Also note that a read in a multiplexed addressing mode (e.g. D16A16ALE) starts
with a write on the EBI_AD lines when it is in the ADDRSETUP state.
Figure 14.21. EBI Enforced IDLE cycles between Transactions
EBI_AD[ 15:8]
EBI_AD[ 7:0]
EBI_CSn
RDSETUP
(0, 1, 2, ...)
RDSTRB
(1, 2, 3, ...)
RDHOLD
(0, 1, 2, ...)
ADDR0[ 7:0]
Z
DATA0[ 7:0]
IDLE
(1, 2, ...)
RDSETUP
(0, 1, 2, ...)
RDSTRB
(1, 2, 3, ...)
ADDR1[ 7:0]
RDHOLD
(0, 1, 2, ...)
Z
DATA1[ 7:0]
EBI_REn
IDLE
(1, 2, ...)
Figure 14.22. EBI No Enforced IDLE cycles between Transactions
RDSETUP
(0, 1, 2, ...)
RDSTRB
(1, 2, 3, ...)
RDHOLD
(0, 1, 2, ...)
RDSETUP
(0, 1, 2, ...)
RDSTRB
(1, 2, 3, ...)
EBI_AD[ 15:8]
ADDR0[ 7:0]
ADDR1[ 7:0]
RDHOLD
(0, 1, 2, ...)
EBI_AD[ 7:0]
EBI_CSn
Z
DATA0[ 7:0]
Z
DATA1[ 7:0]
EBI_REn
Note
In case NOIDLE/NOIDLEn bits are set in EBI_CTRL the read or write strobes can remain
asserted for back-to-back transfers if no further separation is guaranteed via for example
RDSETUP, RDHOLD, WRSETUP, or WRHOLD bitfields.
14.3.10 Timing
The duration of the states in the transaction is defined by the corresponding uppercase name above
the state, e.g. the address setup state in Figure 14.8 (p. 178) is active for a number of internal clock
cycles defined by ADDRSET bitfield in the EBI_ADDRTIMING register. Similar timing can be defined
by the RDSTRB bitfield in the EBI_RDTIMING register and WRSTRB in the EBI_WRTIMING register.
These parameters all have a minimum duration of 1 cycle, which is set by HW in case the bitfield is
programmed to 0.
The setup and hold timing parameters are ADDRHOLD in the EBI_ADDRTIMING register, RDHOLD
and RDSETUP in the EBI_RDTIMING register and WRHOLD and WR SETUP in the EBI_WRTIMING
register. Writing a value m to one of these bitfields results in a duration of the corresponding state of m
cycles. If these parameters are set to 0, it effectively means that the state is skipped.
Page mode access time is defined in the RDPA bitfield of the EBI_PAGECTRL register. This parameters
has a minimum duration of 1 cycle, which is set by HW in case the bitfield is programmed to 0.
When the ITS bitfield in the EBI_CTRL register is set to 0, the timing set defined in the
EBI_ADDRTIMING, EBI_RDTIMING and EBI_WRTIMING registers applies to all 4 memory banks.
When ITS is set to 1 each memory bank uses an individual timing set. In this case registers
EBI_ADDRTIMING, EBI_RDTIMING and EBI_WRTIMING only apply to bank 0. Timing for bank n is
then defined in the EBI_ADDRTIMINGn, EBI_RDTIMINGn and EBI_WRTIMINGn registers.
Note
All timing related bitfields have a default value which is equal to the highest possible value
for these bitfields, which makes the default values a better fit for slow memory devices.
This differs from the EFM32G devices in which the default values correspond to the lowest
possible values, which would only be appropriate for fast memory devices.
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
184
www.energymicro.com