EFM32WG Datasheet, PDF (740/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

31.4 Register Map
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The offset register address is relative to the registers base address.
Offset
0x000
0x004
0x008
0x00C
0x010
0x014
0x018
0x01C
0x020
0x030
0x034
0x038
0x03C
0x040
0x044
0x048
0x04C
Name
AES_CTRL
AES_CMD
AES_STATUS
AES_IEN
AES_IF
AES_IFS
AES_IFC
AES_DATA
AES_XORDATA
AES_KEYLA
AES_KEYLB
AES_KEYLC
AES_KEYLD
AES_KEYHA
AES_KEYHB
AES_KEYHC
AES_KEYHD
Type
RW
W1
R
RW
R
W1
W1
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
31.5 Register Description
31.5.1 AES_CTRL - Control Register
Description
Control Register
Command Register
Status Register
Interrupt Enable Register
Interrupt Flag Register
Interrupt Flag Set Register
Interrupt Flag Clear Register
DATA Register
XORDATA Register
KEY Low Register
KEY Low Register
KEY Low Register
KEY Low Register
KEY High Register
KEY High Register
KEY High Register
KEY High Register
Offset
0x000
Reset
Access
Bit Position
Name
Bit
Name
Reset
Access Description
31:7
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
6
BYTEORDER
0
RW
Configure byte order in data and key registers
When set, the byte orders in the data and key registers are swapped before and after encryption/decryption.
5
XORSTART
0
RW
AES_XORDATA Write Start
Set this bit to start encryption/decryption when DATA3 is written through AES_XORDATA.
4
DATASTART
0
RW
AES_DATA Write Start
Set this bit to start encryption/decryption when DATA3 is written through AES_DATA.
3
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
2
KEYBUFEN
0
RW
Key Buffer Enable
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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