EFM32WG Datasheet, PDF (577/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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22.5.15 BURTC_FREEZE - Freeze Register
Offset
0x038
Reset
Access
Bit Position
Name
Bit
31:1
0
Name
Reset
Access Description
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
REGFREEZE
0
RW
Register Update Freeze
When set, the update of the BURTC is postponed until this bit is cleared. Use this bit to update several registers simultaneously.
Value
0
1
Mode
UPDATE
FREEZE
Description
Each write access to an BURTC register is updated into the Low Frequency domain
as soon as possible.
The BURTC is not updated with the new written value until the freeze bit is cleared.
22.5.16 BURTC_SYNCBUSY - Synchronization Busy Register
Offset
0x03C
Reset
Access
Bit Position
Name
Bit
Name
Reset
Access Description
31:2
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
1
COMP0
0
R
COMP0 Register Busy
Set when the value written to COMP0 is being synchronized.
0
LPMODE
0
R
LPMODE Register Busy
Set when the value written to LPMODE is being synchronized.
22.5.17 RETx_REG - Retention Register
Offset
Bit Position
0x100
Reset
Access
Name
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
577
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