EFM32WG Datasheet, PDF (477/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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Bit
Name
Reset
Access Description
Set to disable transmission.
2
TXEN
0
W1
Transmitter Enable
Set to enable data transmission.
1
RXDIS
0
W1
Receiver Disable
Set to disable data reception. If a frame is under reception when the receiver is disabled, the incoming frame is discarded.
0
RXEN
0
W1
Receiver Enable
Set to activate data reception on U(S)n_RX.
17.5.5 USARTn_STATUS - USART Status Register
Offset
0x010
Reset
Access
Bit Position
Name
Bit
31:13
12
11
10
9
8
7
6
5
4
3
Name
Reset
Access Description
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
RXFULLRIGHT
0
R
RX Full of Right Data
When set, the entire RX buffer contains right data. Only used in I2S mode.
RXDATAVRIGHT
0
R
RX Data Right
When set, reading RXDATA or RXDATAX gives right data. Else left data is read. Only used in I2S mode.
TXBSRIGHT
0
R
TX Buffer Expects Single Right Data
When set, the TX buffer expects at least a single right data. Else it expects left data. Only used in I2S mode.
TXBDRIGHT
0
R
TX Buffer Expects Double Right Data
When set, the TX buffer expects double right data. Else it may expect a single right data or left data. Only used in I2S mode.
RXFULL
0
R
RX FIFO Full
Set when the RXFIFO is full. Cleared when the receive buffer is no longer full. When this bit is set, there is still room for one more
frame in the receive shift register.
RXDATAV
0
R
RX Data Valid
Set when data is available in the receive buffer. Cleared when the receive buffer is empty.
TXBL
1
R
TX Buffer Level
Indicates the level of the transmit buffer. If TXBIL is cleared, TXBL is set whenever the transmit buffer is empty, and if TXBIL is set,
TXBL is set whenever the transmit buffer is half-full or empty.
TXC
0
R
TX Complete
Set when a transmission has completed and no more data is available in the transmit buffer and shift register. Cleared when data
is written to the transmit buffer.
TXTRI
0
R
Transmitter Tristated
Set when the transmitter is tristated, and cleared when transmitter output is enabled. If AUTOTRI in USARTn_CTRL is set this bit
is always read as 0.
RXBLOCK
0
R
Block Incoming Data
When set, the receiver discards incoming frames. An incoming frame will not be loaded into the receive buffer if this bit is set at the
instant the frame has been completely received.
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
477
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