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Table 21.1. RTC Resolution Vs Overflow
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RTC_PRESC
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Resolution
30,5 µs
61,0 µs
122 µs
244 µs
488 µs
977 µs
1,95 ms
3,91 ms
7,81 ms
15,6 ms
31,25 ms
62,5 ms
0,125 s
0,25 s
0,5 s
1s
Overflow
512 s
1024 s
2048 s
1,14 hours
2,28 hours
4,55 hours
9,10 hours
18,2 hours
1,52 days
3,03 days
6,07 days
12,1 days
24,3 days
48,5 days
97,1 days
194 days
21.3.2 Compare Channels
Two compare channels are available in the RTC. The compare values can be set by writing to the RTC
compare channel registers RTC_COMPn, and when RTC_CNT is equal to one of these, the respective
compare interrupt flag COMPn is set.
If COMP0TOP is set, the compare value set for compare channel 0 is used as a top value for the RTC,
and the timer is cleared on a compare match with compare channel 0. If using the COMP0TOP setting,
make sure to set this bit prior to or at the same time the EN bit is set. Setting COMP0TOP after the EN
bit is set may cause unintended operation (i.e. if CNT > COMP0).
21.3.2.1 LETIMER Triggers
A compare event on either of the compare channels can start the LETIMER. See the LETIMER
documentation for more information on this feature.
21.3.2.2 PRS Sources
Both the compare channels of the RTC can be used as PRS sources. They will generate a pulse lasting
one RTC clock cycle on a compare match.
21.3.3 Interrupts
The interrupts generated by the RTC are combined into one interrupt vector. If interrupts for the RTC is
enabled, an interrupt will be made if one or more of the interrupt flags in RTC_IF and their corresponding
bits in RTC_IEN are set. Interrupt events are overflow and compare match on either compare channels.
Clearing of an interrupt flag is performed by writing to the corresponding bit in the RTC_IFC register.
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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