EFM32WG Datasheet, PDF (269/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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}
else if (NAK or XACTERR)
{
Rewind Buffer Pointers
Reset Error Count
Mask ACK
Unmask CHHLTD
Disable Channel
}
else if (CHHLTD)
{
Mask CHHLTD
if (Transfer Done or (Error_count == 3))
{
De-allocate Channel
}
else
{
Re-initialize Channel (in next b_interval - 1 Frame)
}
}
else if (ACK)
{
Reset Error Count
Mask ACK
}
The application is expected to write the data packets into the transmit FIFO when the space is available
in the transmit FIFO and the Request queue up to the count specified in the MC field before switching
to another channel. The application uses the USB_GINTSTS.NPTXFEMP interrupt to find the transmit
FIFO space.
15.4.3.6.10 Interrupt IN Transactions in Slave Mode
To initialize the core after power-on reset, the application must follow the sequence in Overview:
Programming the Core (p. 246) . Before it can communicate with the connected device, it must initialize
a channel as described in Channel Initialization (p. 252) . See Transmit FIFO Write Task in Slave Mode
and Receive FIFO Read Task in Slave Mode for read or write data to and from the FIFO in Slave mode.
A typical interrupt-IN operation in Slave mode is shown in Figure 15.15 (p. 268) . See channel 2 (ch_2).
The assumptions are:
1. The application is attempting to receive one packet (up to 1 maximum packet size) in every frame,
starting with odd. (transfer size = 1,024 bytes).
2. The receive FIFO can hold at least one maximum-packet-size packet and two status DWORDs per
packet (1,031 bytes for FS).
3. Periodic Request Queue depth = 4.
15.4.3.6.10.1 Normal Interrupt IN Operation
The sequence of operations in Figure 15.15 (p. 268) (channel 2) is as follows:
1. Initialize channel 2 as explained in Channel Initialization (p. 252) . The application must set the
USB_HC2_CHAR.ODDFRM bit.
2. Set the USB_HC2_CHAR.CHENA bit to write an IN request to the Periodic Request Queue. For
a high-bandwidth interrupt transfer, the application must write the USB_HC2_CHAR register MC
(maximum number of expected packets in the next frame) times before switching to another channel.
3. The host writes an IN request to the Periodic Request Queue for each USB_HC2_CHAR register
write with a CHENA bit set.
4. The host attempts to send an IN token in the next (odd) frame.
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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