EFM32WG Datasheet, PDF (283/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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15.4.4.1.7 Device DMA/Slave Mode Initialization
The application must meed the following conditions to set up the device core to handle traffic.
• In Slave mode, USB_GINTMSK.NPTXFEMPMSK, and USB_GINTMSK.RXFLVLMSK must be unset.
• In DMA mode, the aforementioned interrupts must be masked.
15.4.4.1.8 Transfer Stop Process
When the core is operating as a device, use the following programing sequence if you want to stop any
transfers (because of an interrupt from the host, typically a reset).
15.4.4.1.8.1 Transfer Stop Programming Flow for IN Endpoints
Sequence of operations:
1. Disable the IN endpoint by programming USB_DIEP0CTL/USB_DIEPx_CTL.EPDIS = 1.
2. Wait for the USB_DIEPx_INT.EPDISBLD interrupt, which indicates that the IN endpoint is completely
disabled. When the EPDISBLD interrupt is asserted, the core clears the following bits:
• USB_DIEP0CTL/USB_DIEPx_CTL.EPDIS = 0
• USB_DIEP0CTL/USB_DIEPx_CTL.EPENA = 0
3. Flush the TX FIFO by programming the following bits:
• USB_GRSTCTL.TXFFLSH = 1
• USB_GRSTCTL.TXFNUM = FIFO number specific to endpoint
4. The application can start polling till USB_GRSTCTL.TXFFLSH is cleared. When this bit is cleared, it
ensures that there is no data left in the TX FIFO.
15.4.4.1.8.2 Transfer Stop Programming Flow for OUT Endpoints
Sequence of operations:
1. Enable all OUT endpoints by setting USB_DOEP0CTL/USB_DOEPx_CTL.EPENA = 1.
2. Before disabling any OUT endpoint, the application must enable Global OUT NAK mode in the core,
according to the instructions in Setting the Global OUT NAK (p. 291) . This ensures that data in the
RX FIFO is sent to the application successfully. Set USB_DCTL.USB_DCTL.SGOUTNAK = 1.
3. Wait for the USB_GINTSTS.GOUTNAKEFF interrupt.
4. Disable all active OUT endpoints by programming the following register bits:
• USB_DOEP0CTL/USB_DOEPx_CTL.EPENA = 1
• USB_DOEP0CTL/USB_DOEPx_CTL.EPDIS = 1
• USB_DOEP0CTL/USB_DOEPx_CTL.SNAK = 1
5. Wait for the USB_DOEP0INT/USB_DOEPx_INT.EPDISBLD interrupt for each OUT endpoint
programmed in the previous step. The USB_DOEP0INT/USB_DOEPx_INT.EPDISBLD interrupt
indicates that the corresponding OUT endpoint is completely disabled. When the EPDISBLD interrupt
is asserted, the core clears the following bits:
• USB_DOEP0CTL/USB_DOEPx_CTL.EPENA = 0
• USB_DOEP0CTL/USB_DOEPx_CTL.EPDIS = 0
Note
The application must not flush the Rx FIFO, as the Global OUT NAK effective interrupt
earlier ensures that there is no data left in the Rx FIFO.
15.4.4.2 Device Programming Operations
Table 15.2 (p. 284) provides links to the programming sequence for different USB transaction types.
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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