EFM32WG Datasheet, PDF (503/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

19.3.8 Transmission Delay
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By configuring TXDELAY in LEUARTn_CTRL, the transmitter can be forced to wait a number of bit-
periods from it is ready to transmit data, to it actually transmits the data. This delay is only applied to the
first frame transmitted after the transmitter has been idle. When transmitting frames back-to-back the
delay is not introduced between the transmitted frames.
This is useful on half duplex buses, because the receiver always returns received frames to software
during the first stop-bit. The bus may still be driven for up to 3 baud periods, depending on the current
frame format. Using the transmission delay, a transmission can be started when a frame is received,
and it is possible to make sure that the transmitter does not begin driving the output before the frame
on the bus is completely transmitted.
19.3.9 PRS RX Input
The LEUART can be configured to receive data directly from the PRS channel by setting RX_PRS in
LEUARTn_INPUT. The PRS channel used can be selected using RX_PRS_SEL in LEUARTn_INPUT.
19.3.10 DMA Support
The LEUART has full DMA support in energy modes EM0 – EM2. The DMA controller can write to the
transmit buffer using the registers LEUARTn_TXDATA and LEUARTn_TXDATAX, and it can read from
receive buffer using the registers LEUARTn_RXDATA and LEUARTn_RXDATAX. This enables single
byte transfers and 9 bit data + control/status bits transfers both to and from the LEUART. The DMA will
start up the HFRCO and run from this when it is waken by the LEUART in EM2. The HFRCO is disabled
once the transaction is done.
A request for the DMA controller to read from the receive buffer can come from one of the following
sources:
• Receive buffer full
A write request can come from one of the following sources:
• Transmit buffer and shift register empty. No data to send.
• Transmit buffer empty
In some cases, it may be sensible to temporarily stop DMA access to the LEUART when a parity or
framing error has occurred. This is enabled by setting ERRSDMA in LEUARTn_CTRL. When this bit is
set, the DMA controller will not get requests from the receive buffer if a framing error or parity error is
detected in the received byte. The ERRSDMA bit applies only to the RX DMA.
When operating in EM2, the DMA controller must be powered up in order to perform the transfer. This
is automatically performed for read operations if RXDMAWU in LEUARTn_CTRL is set and for write
operations if TXDMAWU in LEUARTn_CTRL is set. To make sure the DMA controller still transfers bits
to and from the LEUART in low energy modes, these bits must thus be configured accordingly.
Note
When RXDMAWU or TXDMAWU is set, the system will not be able to go to EM2/EM3
before all related LEUART DMA requests have been processed. This means that if
RXDMAWU is set and the LEUART receives a frame, the system will not be able to go to
EM2/EM3 before the frame has been read from the LEUART. In order for the system to go
to EM2 during the last byte transmission, LEUART_CTRL_TXDMAWU must be cleared in
the DMA interrupt service routine. This is because TXBL will be high during that last byte
transfer.
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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