EFM32WG Datasheet, PDF (63/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

...the world's most energy friendly microcontrollers
• provide a contiguous area of system memory that the controller and host processor can access
• have a base address that is an integer multiple of the total size of the channel control data structure.
Figure 8.6 (p. 63) shows the memory that the controller requires for the channel control data structure,
when all 12 channels and the optional alternate data structure are in use.
Figure 8.6. Memory map for 12 channels, including the alternate data structure
Alternate data structure
Prim ary dat a st ruct ure
Alt ernat e_Ch_11
Alt ernat e_Ch_10
Alt ernat e_Ch_9
Alt ernat e_Ch_8
Alt ernat e_Ch_7
Alt ernat e_Ch_6
Alt ernat e_Ch_5
Alt ernat e_Ch_4
Alt ernat e_Ch_3
Alt ernat e_Ch_2
Alt ernat e_Ch_1
Alt ernat e_Ch_0
0 x 1 C0
0 x 1 B0
0 x 1 A0
0x190
0x180
0x170
0x160
0x150
0x140
0x130
0x120
0x110
0x100
Prim ary_Ch_11
Prim ary_Ch_10
Prim ary_Ch_9
Prim ary_Ch_8
Prim ary_Ch_7
Prim ary_Ch_6
Prim ary_Ch_5
Prim ary_Ch_4
Prim ary_Ch_3
Prim ary_Ch_2
Prim ary_Ch_1
Prim ary_Ch_0
0 x 0 C0
0 x 0 B0
0 x 0 A0
0x090
0x080
0x070
0x060
0x050
0x040
0x030
0x020
0x010
0x000
User
Cont rol
Dest inat ion End Point er
Source End Point er
0x00C
0x008
0x004
0x000
This structure in Figure 8.6 (p. 63) uses 384 bytes of system memory. The controller uses the lower
8 address bits to enable it to access all of the elements in the structure and therefore the base address
must be at 0xXXXXXX00.
You can configure the base address for the primary data structure by writing the appropriate value in
the DMA_CTRLBASE register.
You do not need to set aside the full 384 bytes if all dma channels are not used or if all alternate
descriptors are not used. If, for example, only 4 channels are used and they only need the primary
descriptors, then only 64 bytes need to be set aside.
Table 8.6 (p. 63) lists the address bits that the controller uses when it accesses the elements of the
channel control data structure.
Table 8.6. Address bit settings for the channel control data structure
Address bits
[8]
[7]
[6]
[5]
[4]
[3:0]
A
C[3]
C[2]
C[1]
C[0]
0x0, 0x4, or 0x8
Where:
A
C[3:0]
Selects one of the channel control data structures:
A = 0 Selects the primary data structure.
A = 1 Selects the alternate data structure.
Selects the DMA channel.
Address[3:0]
Selects one of the control elements:
0x0 Selects the source data end pointer.
0x4 Selects the destination data end pointer.
0x8 Selects the control data configuration.
0xC The controller does not access this address location. If required, you can
enable the host processor to use this memory location as system memory.
Note
It is not necessary for you to calculate the base address of the alternate data structure
because the DMA_ALTCTRLBASE register provides this information.
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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