EFM32WG Datasheet, PDF (379/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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Bit
Name
Reset
Access Description
31:0
DMAADDR
0xXXXXXXXX RW
DMA Address
This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must
be stored. This register is incremented on every AHB transaction. The data for this register field is stored in RAM. Thus, the reset
value is undefined (X).
15.6.40 USB_DCFG - Device Configuration Register
This register configures the core in Device mode after power-on or after certain control commands or
enumeration. Do not make changes to this register after initial programming.
Offset
0x3C800
Reset
Bit Position
Access
Name
Bit
31:26
25:13
12:11
10:4
3
2
1:0
Name
Reset
Access Description
RESVALID
0x02
RW
Resume Validation Period
This field is effective only when USB_DCFG.ENA32KHZSUSP is set. It will control the resume period when the core resumes from
suspend. The core counts for RESVALID number of clock cycles to detect a valid resume when USB_DCFG.ENA32KHZSUSP is set.
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
PERFRINT
0x0
RW
Periodic Frame Interval
Indicates the time within a frame at which the application must be notified using the End Of Periodic Frame Interrupt. This can be
used to determine if all the isochronous traffic for that frame is complete.
Value
0
1
2
3
Mode
80PCNT
85PCNT
90PCNT
95PCNT
Description
80% of the frame interval.
85% of the frame interval.
90% of the frame interval.
95% of the frame interval.
DEVADDR
0x00
RW
Device Address
The application must program this field after every SetAddress control command.
ENA32KHZSUSP
0
RW
Enable 32 KHz Suspend mode
When this bit is set, the core expects that the PHY clock during Suspend is switched from 48 MHz to 32 KHz.
NZSTSOUTHSHK
0
RW
Non-Zero-Length Status OUT Handshake
The application can use this field to select the handshake the core sends on receiving a nonzero-length data packet during the OUT
transaction of a control transfer's Status stage. When set to 1 send a STALL handshake on a nonzero-length status OUT transaction
and do not send the received OUT packet to the application. When set to 0 send the received OUT packet to the application (zerolength
or nonzero-length) and send a handshake based on the NAK and STALL bits for the endpoint in the Device Endpoint Control register.
DEVSPD
0x0
RW
Device Speed
Indicates the speed at which the application requires the core to enumerate, or the maximum speed the application can support.
However, the actual bus speed is determined only after the chirp sequence is completed, and is based on the speed of the USB
host to which the core is connected.
Value
2
3
Mode
LS
FS
Description
Low speed (PHY clock is 6 MHz). If you select 6 MHz LS mode, you must do a soft
reset.
Full speed (PHY clock is 48 MHz).
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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