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14.3.11 Data Access Width
The mapping of AHB transactions to external device accesses depends on the data width of the external
device and on whether or not it supports byte lanes. The data width of external devices is specified in
the MODE and MODEn bitfields of the EBI_CTRL register. An external device is specified to be either
8-bit or 16-bit wide. Availability of byte lane support by the external device is specified via the BL and
BLn bitfields of the EBI_CTRL register. When the ITS bitfield in the EBI_CTRL register is set to 0, the
MODE and BL bitfields apply to all 4 memory banks. When ITS is set to 1 each memory bank uses an
individual mode and byte lane enable definition. In this case bitfields MODE and BL only apply to bank
0. The mode and byte lane availability for bank n is then defined in the MODEn and BLn bitfields.
In case the AHB transaction width does not match the width of the selected device, the EBI automatically
translates the AHB transaction into 1 or more external device transactions matching the capabilities
of that device. If one AHB transaction is translated into multiple external transactions, then the
external transactions have incrementing addresses and start with the lowest data byte(s) from the AHB
transaction. The translation, and possibly bus fault generation, is explained below and in Table 14.3 (p.
185) :
• If the AHB transaction width is larger than the external device width, then multiple consecutive external
transactions are performed starting with the least significant data.
• If the AHB transaction width is smaller than the external device width, then EBI behavior depends on
whether or not byte lanes are available for the selected device. Reads either use byte lane support
when available, or read according to the full external device width and disregard the superfluous data.
Writes normally either use byte lane support when available, or perform a read-modify-write sequence
to only change the required data. However, NAND Flash does not support byte lanes or random
access read-modify-write and therefore a hard fault is generated in case of an 8-bit write to a bank
designated as 16-bit NAND bank.
Table 14.3. EBI Mapping of AHB Transactions to External Device Transactions
Data Access
by Cortex-
M4, DMA, or
prefetch
8-bit read
16-bit read
32-bit read
8-bit write
16-bit write
32-bit write
8-bit External
Device (non-
NAND)
transaction(s)
1 x 8-bit read
2 x 8-bit read
4 x 8-bit read
1 x 8-bit write
2 x 8-bit write
4 x 8-bit write
16-bit External
Device (non-
NAND)
transaction(s)
(with byte lanes)
1 x 8-bit read
(using byte lane)
1 x 16-bit read
2 x 16-bit read
1 x 8-bit write
(using byte lane)
1 x 16-bit write
2 x 16-bit write
16-bit External
Device (non-
NAND)
transaction(s)
(without byte
lanes)
1 x 16-bit read
1 x 16-bit read
2 x 16-bit read
1 x 16-bit read;
1 x 16-bit write
(read-modify-
write)
1 x 16-bit write
2 x 16-bit write
8-bit NAND Flash 16-bit
transaction(s)
NAND Flash
transaction(s)
1 x 8-bit read
2 x 8-bit read
4 x 8-bit read
1 x 8-bit write
1 x 16-bit read
1 x 16-bit read
2 x 16-bit read
- (Hard fault)
2 x 8-bit write
4 x 8-bit write
1 x 16-bit write
2 x 16-bit write
14.3.12 Bank Access
The EBI is split in 4 different address regions, each connected to an individual EBI_CSn line. When
accessing one of the memory regions, the corresponding CSn line is asserted. This way up to 4 separate
devices can share the EBI lines and be identified by the EBI_CSn line. Each bank can individually be
enabled or disabled in the EBI_CTRL register.
The bank separation depends on whether the access originates from code space or not and on the
setting of the ALTMAP bit in the EBI_CTRL register. From code space three 32 MB banks and one 128
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