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• In all the above three cases, the packet count is not decremented because no data is written to
the receive FIFO.
3. When the packet count becomes 0 or when a short packet is received on the endpoint, the NAK bit
for that endpoint is set. Once the NAK bit is set, the isochronous or non-isochronous data packets
are ignored and not written to the receive FIFO, and non-isochronous OUT tokens receive a NAK
handshake reply.
4. After the data is written to the receive FIFO, either the application (in Slave mode) or the core’s DMA
engine (in DMA mode), reads the data from the receive FIFO and writes it to external memory, one
packet at a time per endpoint.
5. At the end of every packet write on the AHB to external memory, the transfer size for the endpoint
is decremented by the size of the written packet.
6. The OUT Data Transfer Completed pattern for an OUT endpoint is written to the receive FIFO on
one of the following conditions.
• The transfer size is 0 and the packet count is 0
• The last OUT data packet written to the receive FIFO is a short packet (0 <= packet size < maximum
packet size)
7. When either the application or the DMA pops this entry (OUT Data Transfer Completed), a Transfer
Completed interrupt is generated for the endpoint and the endpoint enable is cleared.
Application Programming Sequence
1. Program the USB_DOEPx_TSIZ register for the transfer size and the corresponding packet count.
Additionally, in DMA mode, program the USB_DOEPx_DMAADDR register.
2. Program the USB_DOEPx_CTL register with the endpoint characteristics, and set the Endpoint
Enable and ClearNAK bits.
• USB_DOEPx_CTL.EPENA = 1
• USB_DOEPx_CTL.CNAK = 1
3. In Slave mode, wait for the USB_GINTSTS.RXFLVL level interrupt and empty the data packets from
the receive FIFO as explained in Packet Read from FIFO in Slave Mode (p. 290) .
• This step can be repeated many times, depending on the transfer size.
4. Asserting the USB_DOEPx_INT.XFERCOMPL interrupt marks a successful completion of the non-
isochronous OUT data transfer.
5. Read the USB_DOEPx_TSIZ register to determine the size of the received data payload.
Note
The XFERSIZE is not decremented for the last packet. This is as per design behavior.
Slave Mode Bulk OUT Transaction
Figure 15.22 (p. 295) depicts the reception of a single bulk OUT data packet from the USB to the AHB
and describes the events involved in the process.
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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