EFM32WG Datasheet, PDF (553/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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20.5.19 TIMERn_DTOGEN - DTI Output Generation Enable Register
Offset
0x07C
Reset
Access
Bit Position
Name
Bit
Name
Reset
Access Description
31:6
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
5
DTOGCDTI2EN
0
RW
DTI CDTI2 Output Generation Enable
This bit enables/disables output generation for the CDTI2 output from the DTI.
4
DTOGCDTI1EN
0
RW
DTI CDTI1 Output Generation Enable
This bit enables/disables output generation for the CDTI1 output from the DTI.
3
DTOGCDTI0EN
0
RW
DTI CDTI0 Output Generation Enable
This bit enables/disables output generation for the CDTI0 output from the DTI.
2
DTOGCC2EN
0
RW
DTI CC2 Output Generation Enable
This bit enables/disables output generation for the CC2 output from the DTI.
1
DTOGCC1EN
0
RW
DTI CC1 Output Generation Enable
This bit enables/disables output generation for the CC1 output from the DTI.
0
DTOGCC0EN
0
RW
DTI CC0 Output Generation Enable
This bit enables/disables output generation for the CC0 output from the DTI.
20.5.20 TIMERn_DTFAULT - DTI Fault Register
Offset
0x080
Reset
Access
Bit Position
Name
Bit
Name
Reset
Access Description
31:4
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
3
DTLOCKUPF
0
R
DTI Lockup Fault
This bit is set to 1 if a core lockup fault has occurred and DTLOCKUPFEN is set to 1. The TIMER0_DTFAULTC register can be
used to clear fault bits.
2
DTDBGF
0
R
DTI Debugger Fault
This bit is set to 1 if a debugger fault has occurred and DTDBGFEN is set to 1. The TIMER0_DTFAULTC register can be used to
clear fault bits.
1
DTPRS1F
0
R
DTI PRS 1 Fault
This bit is set to 1 if a PRS 1 fault has occurred and DTPRS1FEN is set to 1. The TIMER0_DTFAULTC register can be used to
clear fault bits.
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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