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lower 8 address bits are always output on EBI_AD. Therefore, if address extension is required, only
address bits 8 and upwards need to be enabled on EBI_A. This is done by setting the EBI_A lower
bound to 8 by setting ALB to A8 in EBI_ROUTE and by enabling the required higher address lines via the
APEN bitfield in EBI_ROUTE. The operation of the APEN and ALB bitfields is shown in Table 14.2 (p.
182) for some typical configurations.
Table 14.2. EBI Enabling EBI_ADDR lines for transaction with address Addr and data Data
Configuration
Addresses on EBI_A
MODE = D8A8, ALB = A8, APEN =
A28
EBI_A[27:8] = Addr[27:8]
MODE = D16A16ALE, ALB = A16,
APEN = A27
EBI_A[26:16] = Addr[27:17]
MODE = D8A24ALE, ALB = A24,
APEN = A28
EBI_A[27:24] = Addr[27:24]
MODE = D16, ALB = A0, APEN = A27 EBI_A[26:0] = Addr[27:1]
Addresses/data on EBI_AD
EBI_AD[15:0] = {Addr[7:0], Data[7:0]}
EBI_AD[15:0] = Addr[16:1]; Data[15:0]
EBI_AD[15:0] = Addr[23:8]; {Addr[7:0],
Data[7:0]}
EBI_AD[15:0] = Data[15:0]
14.3.7 Prefetch Unit and Write Buffer
Prefetching from external memory can enhance the performance of a sequence of consecutive transfers.
In particular sequential code execution from external memory can benefit from prefetch. Also prefetch will
typically lead to better utilization of intrapage accesses in case page mode is used. If prefetch is enabled,
the prefetch unit will sequentially prefetch one data item of the same width as the last Cortex-M4 or DMA
read transaction handled by the EBI. Note that one prefetch transaction might lead to multiple external
device transactions as described in Table 14.3 (p. 185) . Prefetch is not performed in reaction to write
transactions, nor will prefetch cross bank boundaries. The prefetch unit is enabled via the PREFETCH
bitfield in the EBI_RDTIMING and EBI_RDTIMINGn registers. When the ITS bitfield in the EBI_CTRL
register is set to 0, the PREFETCH bitfield from EBI_RDTIMING applies to all 4 memory banks. When
ITS is set to 1 the prefetch unit can be individually enabled per bank. In this case register EBI_RDTIMING
only applies to bank 0. Prefetch enabling for bank n is then defined in the EBI_RDTIMINGn register.
The EBI has a 1 entry 32-bit wide write buffer. The write buffer can be used to limit stalling by partially
decoupling the Cortex-M4 or DMA from a potentially slow external device. Only writes which are
guaranteed to not cause an error (e.g. timeout) in the EBI will be buffered when the write buffer is
enabled, such that precise error generation is guaranteed. The write buffer is disabled via the WBUFDIS
bitfield in the EBI_WRTIMING and EBI_WRTIMINGn registers. When the ITS bitfield in the EBI_CTRL
register is set to 0, the WBUFDIS bitfield from EBI_WRTIMING applies to all 4 memory banks. When ITS
is set to 1 the write buffer can be individually disabled per bank. In this case register EBI_WRTIMING
only applies to bank 0. Write buffer disabling for bank n is then defined in the EBI_WRTIMINGn register.
The AHBACT status bit in the EBI_STATUS register indicates whether an AHB transaction is still active
in the EBI or not. When performing an AHB write, the AHBACT bit stays 1 until the required transaction(s)
with the external device have finished, independent of whether the AHB write gets buffered or not. On
an AHB read with prefetching enabled, AHBACT stays high until the potential external device prefetch
transaction(s) have finished.
14.3.8 Strobe length
For external devices with low, but non-zero, setup requirements the performance overhead for EBI
transactions can be relatively large if a full cycle setup time needs to be used. It is possible to borrow
half of the cycle time from a neighboring strobe phase in order to define setup times with a granularity
of half the internal clock period.
The durations of the EBI_ALE, EBI_REn, EBI_WEn, EBI_NANDREn and EBI_NANDWEn strobes can
be individually decreased by half the internal clock period via the HALFALE, HALFRE and HALFWE
bitfields in the address timing, read timing and write timing registers respectively. In case of EBI_ALE
the trailing edge of the strobe can be moved half a clock period earlier. In case of EBI_REn, EBI_WEn,
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