EFM32WG Datasheet, PDF (203/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

...the world's most energy friendly microcontrollers
External masking is enabled by setting the EMASK bit in the EBI_TFTCTRL register to 1. If enabled,
writes to the memory bank defined in the BANKSEL bitfield of the EBI_TFTCTRL register are suppressed
in case the write data matches the value in EBI_TFTMASK.
Internal masking is enabled by setting the IMASK bit in the EBI_TFTCTRL register to 1. If enabled
and EBI_TFTPIXEL0 is written with data matching EBI_TFTMASK, then the background color from
EBI_TFTPIXEL1 is copied into EBI_TFTPIXEL. If enabled and EBI_TFTPIXEL0 is written with data
not matching EBI_TFTMASK, then the color from EBI_TFTPIXEL0 (possibly alpha blended with
EBI_TFTPIXEL1) is written into EBI_TFTPIXEL. The three DMA requests and EBI_STATUS bits as
described for internal alpha blending also apply for internal masking.
14.3.18 Direct Drive Timing
The timing definition for operating a TFT display in Direct Drive mode depends on where the frame buffer
source is located. In case internal memory is used as source, then only the TFT timing as defined in the
EBI_TFTTIMING register is relevant. In case external memory is used as the source memory, then both
the timing parameters of the TFT display and the timing parameters of the memory bank defined in the
BANKSEL bitfield of the EBI_TFTCTRL register are relevant.
The minimum dot clock, EBI_DCLK, period is defined in the DCLKPERIOD bitfield of the
EBI_TFTTIMING register. This parameter has a minimum duration of 1 cycle, which is set by HW, and
writing a value n to this bitfield results in an extended duration of 1+n cycles. At cycle 0 (and then
periodically with period DCLKPERIOD + 1) the EBI_DCLK inactive edges are generated. At the cycle
defined in the TFTSTART bitfield of the EBI_TFTTIMING the TFT Direct Drive transaction is started. The
TFTSTART bitfield can be used to define the duty cycle of the EBI_DCLK. This parameter has a minimum
duration of 1 cycle, which is set by HW, and writing a value n to this bitfield results in an extended
duration of 1+n cycles. After performing the required actions to produce the required TFT pixel data on
the EBI_AD lines, the TFT transaction will pass through its TFTSETUP and TFTHOLD states as indicated
in Figure 14.39 (p. 204) . In this figure, the duration of the states in the TFT transaction is defined by
the corresponding uppercase name above the state and it is expressed in internal clock cycles. The TFT
setup and hold times are set in the TFTHOLD and TFTSETUP bitfields in the EBI_TFTTIMING register.
Writing a value m to one of these bitfields results in a duration of the corresponding state of m internal
clock cycles. If these parameters are set to 0, it effectively means that the state is skipped. The TFT
setup and hold timing is with respect to the active edge of EBI_DCLK as defined in the DCLKPOL bitfield
in the EBI_TFTPOLARITY register. The TFT setup and hold timing applies to all TFT signals: EBI_AD,
EBI_DATAEN, EBI_VSYNC, EBI_HSYNC and EBI_TFTCSn. The active EBI_DCLK edge is generated
in between the TFTSETUP and TFTHOLD states. The TFTSTART bitfield therefore impacts the position
of the active EBI_DCLK edge. The later the TFT transaction is started, the later it will transition from
its TFTSETUP to TFTHOLD state. If needed, the EBI_DCLK period is automatically stretched beyond
the DCLKPERIOD to complete the TFT transaction. EBI_DCLK period stretching occurs when the TFT
transaction does not complete in the specified time, which in turn can occur because of the following
reasons:
• Specified timing parameters are conflicting. This can for example happen if the TFT setup plus hold
time is programmed to be longer than the EBI_DCLK period.
• TFT transaction is delayed by an ongoing EBI transaction. This transaction interference can
be controlled by setting the transaction interleaving strategy in the INTERLEAVE bitfield of the
EBI_TFTCTRL register.
• TFT transaction data is not delivered in time. For internal Direct Drive this is caused by the Cortex-M4
or DMA not delivering the data in time. For external Direct Drive the timing parameters defining the
external device read access might not allow the TFT transaction to complete in time.
In case the specified DCLK_PERIOD is not met, the DDJIT interrupt flag in the EBI_IF register will be set.
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
203
www.energymicro.com