English
Language : 

EFM32WG Datasheet, PDF (401/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.
...the world's most energy friendly microcontrollers
Bit
30:29
28:19
18:0
Name
Reset
Access Description
RXDPIDSUPCNT
0x0
R
Receive Data PID / SETUP Packet Count
For isochronous OUT endpoints: This is the data PID received in the last packet for this endpoint.
For control OUT Endpoints: This field specifies the number of back-to-back SETUP data packets the endpoint can receive.
Value
0
1
2
3
Mode
DATA0
DATA2
DATA1
MDATA
Description
DATA0 PID.
DATA2 PID / 1 Packet.
DATA1 PID / 2 Packets.
MDATA PID / 3 Packets.
PKTCNT
0x000
RW
Packet Count
This field is decremented to zero after a packet is written into the RxFIFO.
XFERSIZE
0x00000
RW
Transfer Size
Indicates the transfer size in bytes. The core interrupts the application only after it has exhausted the transfer size amount of data.
The transfer size can be set to the maximum packet size of the endpoint, to be interrupted at the end of each packet. The core
decrements this field every time a packet is read from the RxFIFO and written to the external memory.
15.6.67 USB_DOEPx_DMAADDR - Device OUT Endpoint x+1 DMA Address
Register
Offset
0x3CB34
Bit Position
Reset
Access
Name
Bit
Name
Reset
Access Description
31:0
DMAADDR
0xXXXXXXXX RW
DMA Address
Holds the start address of the external memory for storing endpoint data. For control endpoints, this field stores control OUT data
packets as well as SETUP transaction data packets. When more than three SETUP packets are received back-to-back, the SETUP
data packet in the memory is overwritten. This register is incremented on every AHB transaction. The application can give only a
DWORD-aligned address. The data for this register field is stored in RAM. Thus, the reset value is undefined (X).
15.6.68 USB_PCGCCTL - Power and Clock Gating Control Register
This register is available in Host and Device modes. The application use this register to control the core's
power-down and clock gating features.
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
401
www.energymicro.com