EFM32WG Datasheet, PDF (137/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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Bit
Name
Reset
Access Description
Set this to configure the external source for the HFXO. The oscillator setting takes effect when 1 is written to HFXOEN in
CMU_OSCENCMD. The oscillator setting is reset to default when 1 is written to HFXODIS in CMU_OSCENCMD.
Value
0
1
2
Mode
XTAL
BUFEXTCLK
DIGEXTCLK
Description
4-32 MHz crystal oscillator.
An AC coupled buffer is coupled in series with HFXTAL_N, suitable for external sine
wave (4-32 MHz). The sine wave should have a minimum of 200 mV peak to peak.
Digital external clock on HFXTAL_N pin. Oscillator is effectively bypassed.
11.5.2 CMU_HFCORECLKDIV - High Frequency Core Clock Division
Register
Offset
0x004
Reset
Access
Bit Position
Name
Bit
31:9
8
7:4
3:0
Name
Reset
Access Description
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
HFCORECLKLEDIV
0
RW
Additional Division Factor For HFCORECLKLE
Additional division factor for HFCORECLKLE. When running at frequencies higher than 24 MHz, this must be set to DIV4.
Value
0
1
Mode
DIV2
DIV4
Description
Valid for frequencies 24 MHz and lower.
Must be used when HFCORECLK may go above 24 MHz.
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
HFCORECLKDIV
0x0
RW
Specifies the clock divider for HFCORECLK.
HFCORECLK Divider
Value
0
1
2
3
4
5
6
7
8
9
Mode
HFCLK
HFCLK2
HFCLK4
HFCLK8
HFCLK16
HFCLK32
HFCLK64
HFCLK128
HFCLK256
HFCLK512
Description
HFCORECLK = HFCLK.
HFCORECLK = HFCLK/2.
HFCORECLK = HFCLK/4.
HFCORECLK = HFCLK/8.
HFCORECLK = HFCLK/16.
HFCORECLK = HFCLK/32.
HFCORECLK = HFCLK/64.
HFCORECLK = HFCLK/128.
HFCORECLK = HFCLK/256.
HFCORECLK = HFCLK/512.
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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