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15.4.2.3.2 Pipelined Transaction-Level Operation
The application can pipeline more than one transaction (IN or OUT) with pipelined transaction-level
operation, which is analogous to Transfer mode in DMA mode. In pipelined transaction-level operation,
the application can program the core to perform multiple transactions. The advantage of this mode
compared to transaction-level operation is that the application is not interrupted on a packet basis.
15.4.2.3.2.1 Host mode
For an OUT transaction, the application sets up a transfer and enables the channel. The application can
write multiple packets back-to-back for the same channel into the transmit FIFO, based on the space
availability. It can also pipeline OUT transactions for multiple channels by writing into the HCHARn
register, followed by a packet write to that channel. The core writes the channel number, along with the
last DWORD write for the packet, into the Request queue and schedules transactions on the USB in
the same order.
For an IN transaction, the application sets up a transfer and enables the channel, and the core writes
the channel number into the Request queue. The application can schedule IN transactions on multiple
channels, provided space is available in the Request queue. The core initiates an IN token on the USB
only when there is enough space to receive at least of one maximum-packet-size packet of the channel
in the top of the Request queue.
15.4.2.3.2.2 Device mode
For an IN transaction, the application sets up a transfer and enables the endpoint. The application can
write multiple packets back-to-back for the same endpoint into the transmit FIFO, based on available
space. It can also pipeline IN transactions for multiple channels by writing into the USB_DIEPx_CTL
register followed by a packet write to that endpoint. The core writes the endpoint number, along with the
last DWORD write for the packet into the Request queue. The core transmits the data in the transmit
FIFO when an IN token is received on the USB.
For an OUT transaction, the application sets up a transfer and enables the endpoint. The core receives
the OUT data into the receive FIFO, when it has available space. As the packets are received into the
FIFO, the application must empty data from it.
From this point on in this chapter, the terms “Pipelined Transaction mode” and “Transfer mode” are used
interchangeably.
15.4.3 Host Programming Model
Before you program the Host, read Overview: Programming the Core (p. 246) and Modes of
operation (p. 249) .
This section discusses the following topics:
• Channel Initialization (p. 252)
• Halting a Channel (p. 253)
• Zero-Length Packets (p. 254)
• Handling Babble Conditions (p. 254)
• Handling Disconnects (p. 254)
• Host Programming Operations (p. 254)
• Writing the Transmit FIFO in Slave Mode (p. 255)
• Reading the Receive FIFO in Slave Mode (p. 256)
15.4.3.1 Channel Initialization
The application must initialize one or more channels before it can communicate with connected devices.
To initialize and enable a channel, the application must perform the following steps.
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