EFM32WG Datasheet, PDF (580/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

• Repeat done
• Optionally runs during debug
...the world's most energy friendly microcontrollers
23.3 Functional Description
An overview of the LETIMER module is shown in Figure 23.1 (p. 580) . The LETIMER is a
16-bit down-counter with two compare registers, LETIMERn_COMP0 and LETIMERn_COMP1. The
LETIMERn_COMP0 register can optionally act as a top value for the counter. The repeat counter
LETIMERn_REP0 allows the timer to count a specified number of times before it stops. Both the
LETIMERn_COMP0 and LETIMERn_REP0 registers can be double buffered by the LETIMERn_COMP1
and LETIMERn_REP1 registers to allow continuous operation. The timer can generate a single pin
output, or two linked outputs.
Figure 23.1. LETIMER Overview
RTC event
SW
LFACLK_LETIMERn
LETIMER Cont rol
and St at us
St art
COMP1
(Top Buffer)
Updat e
COMP0
( To p )
Reload
Top load
logic
CNT (Count er)
=0
St op
0
REP0
(Repeat )
=1
Updat e
Buffer
Re p e a t
Written
load logic
REP1
(Repeat Buffer)
=1
=
COMP1 Mat ch
(COMP1 int errupt flag)
=
COMP0 Mat ch
(COMP0 int errupt flag)
Underflow
(UF int errupt flag)
Pu l se
pin
Cont rol
ctrl
LETn _O0
Pu l se
pin
Cont rol
ctrl
LETn _O1
REP0 Zero
(REP0 int errupt flag)
REP1 Zero
(REP1 int errupt flag)
23.3.1 Timer
The timer is started by setting command bit START in LETIMERn_CMD, and stopped by setting the
STOP command bit in the same register. RUNNING in LETIMERn_STATUS is set as long as the timer is
running. The timer can also be started on external signals, such as a compare match from the Real Time
Counter. If START and STOP are set at the same time, STOP has priority, and the timer will be stopped.
The timer value can be read using the LETIMERn_CNT register. The value cannot be written, but it
can be cleared by setting the CLEAR command bit in LETIMERn_CMD. If the CLEAR and START
commands are issued at the same time, the timer will be cleared, then start counting at the top value.
23.3.2 Compare Registers
The LETIMER has two compare match registers, LETIMERn_COMP0 and LETIMERn_COMP1.
Each of these compare registers are capable of generating an interrupt when the counter value
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
580
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