EFM32WG Datasheet, PDF (135/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

11.5 Register Description
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11.5.1 CMU_CTRL - CMU Control Register
Offset
0x000
Reset
Access
Bit Position
Name
Bit
31
30
29
28
27:26
25:23
22:20
19:18
Name
Reset
Access Description
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
HFLE
0
RW
High-Frequency LE Interface
Set to allow access to LE peripherals when running at frequencies higher than 32 MHz.
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
DBGCLK
0
RW
Select clock used for the debug system.
Debug Clock
Value
0
1
Mode
AUXHFRCO
HFCLK
Description
AUXHFRCO is the debug clock.
The system clock is the debug clock.
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
CLKOUTSEL1
0x0
RW
Clock Output Select 1
Controls the clock output multiplexer. To actually output on the pin, set CLKOUT1PEN in CMU_ROUTE.
Value
0
1
2
3
4
5
6
7
Mode
LFRCO
LFXO
HFCLK
LFXOQ
HFXOQ
LFRCOQ
HFRCOQ
AUXHFRCOQ
Description
LFRCO (directly from oscillator).
LFXO (directly from oscillator).
HFCLK.
LFXO (qualified).
HFXO (qualified).
LFRCO (qualified).
HFRCO (qualified).
AUXHFRCO (qualified).
CLKOUTSEL0
0x0
RW
Clock Output Select 0
Controls the clock output multiplexer. To actually output on the pin, set CLKOUT0PEN in CMU_ROUTE.
Value
0
1
2
3
4
5
6
7
Mode
HFRCO
HFXO
HFCLK2
HFCLK4
HFCLK8
HFCLK16
ULFRCO
AUXHFRCO
Description
HFRCO (directly from oscillator).
HFXO (directly from oscillator).
HFCLK/2.
HFCLK/4.
HFCLK/8.
HFCLK/16.
ULFRCO (directly from oscillator).
AUXHFRCO (directly from oscillator).
LFXOTIMEOUT
0x3
RW
Configures the start-up delay for LFXO.
LFXO Timeout
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
135
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