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2. In Slave mode, the application must also write the required data to the associated transmit FIFO for
the endpoint. In DMA mode, the core fetches the data for the endpoint from memory, according to
the application setting.
3. Every time either the core’s internal DMA (in DMA mode) or the application (in Slave mode) writes a
packet to the transmit FIFO, the transfer size for that endpoint is decremented by the packet size. The
data is fetched from DMA or application memory until the transfer size for the endpoint becomes 0.
4. When an IN token is received for an periodic endpoint, the core transmits the data in the FIFO, if
available. If the complete data payload (complete packet) for the frame is not present in the FIFO,
then the core generates an IN Token Received When TxFIFO Empty Interrupt for the endpoint.
• A zero-length data packet is transmitted on the USB for isochronous IN endpoints
• A NAK handshake is transmitted on the USB for interrupt IN endpoints
5. The packet count for the endpoint is decremented by 1 under the following conditions:
• For isochronous endpoints, when a zero- or non-zero-length data packet is transmitted
• For interrupt endpoints, when an ACK handshake is transmitted
• When the transfer size and packet count are both 0, the Transfer Completed interrupt for the
endpoint is generated and the endpoint enable is cleared.
6. At the “Periodic frame Interval” (controlled by USB_DCFG.PERFRINT), when the core finds non-
empty any of the isochronous IN endpoint FIFOs scheduled for the current frame non-empty, the core
generates a USB_GINTSTS.INCOMPISOIN interrupt.
Application Programming Sequence (Transfer Per Frame)
1. Program the USB_DIEPx_TSIZ register. In DMA mode, also program the USB_DIEPx_DMAADDR
register.
2. Program the USB_DIEPx_CTL register with the endpoint characteristics and set the CNAK and
Endpoint Enable bits.
3. In Slave mode, write the data to be transmitted in the next frame to the transmit FIFO.
4. Asserting the USB_DIEPx_INT.INTKNTXFEMP (In Token Received When TxFifo Empty) interrupt
indicates that either the DMA or application has not yet written all data to be transmitted to the transmit
FIFO.
5. If the interrupt endpoint is already enabled when this interrupt is detected, ignore the interrupt. If it is
not enabled, enable the endpoint so that the data can be transmitted on the next IN token attempt.
• If the isochronous endpoint is already enabled when this interrupt is detected, see Incomplete
Isochronous IN Data Transfers (p. 305) for more details.
6. The core handles timeouts internally on interrupt IN endpoints programmed as periodic endpoints
without application intervention. The application, thus, never detects a USB_DIEPx_INT.TIMEOUT
interrupt for periodic interrupt IN endpoints.
7. Asserting the USB_DIEPx_INT.XFERCOMPL interrupt with no USB_DIEPx_INT.INTKNTXFEMP (In
Token Received When TxFifo Empty) interrupt indicates the successful completion of an isochronous
IN transfer. A read to the USB_DIEPx_TSIZ register must indicate transfer size = 0 and packet
count = 0, indicating all data is transmitted on the USB.
8. Asserting the USB_DIEPx_INT.XFERCOMPL interrupt, with or without the
USB_DIEPx_INT.INTKNTXFEMP (In Token Received When TxFifo Empty) interrupt, indicates the
successful completion of an interrupt IN transfer. A read to the USB_DIEPx_TSIZ register must
indicate transfer size = 0 and packet count = 0, indicating all data is transmitted on the USB.
9. Asserting the USB_GINTSTS.INCOMPISOIN (Incomplete Isochronous IN Transfer) interrupt with
none of the aforementioned interrupts indicates the core did not receive at least 1 periodic IN token
in the current frame.
10.For isochronous IN endpoints, see Incomplete Isochronous IN Data Transfers (p. 305) , for more
details.
15.4.4.2.3.14 Generic Periodic IN Data Transfers Using the Periodic Transfer Interrupt Feature
This section describes a typical Periodic IN (ISOC / INTR) data transfer with the Periodic Transfer
Interrupt feature.
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