EFM32WG Datasheet, PDF (298/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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• If there is no space in the receive FIFO, interrupt data packets are ignored and not written to the
receive FIFO. Additionally, interrupt OUT tokens receive a NAK handshake reply.
2. When the packet count becomes 0 or when a short packet is received on the endpoint, the NAK bit
for that endpoint is set. Once the NAK bit is set, the isochronous or interrupt data packets are ignored
and not written to the receive FIFO, and interrupt OUT tokens receive a NAK handshake reply.
3. After the data is written to the receive FIFO, the core’s DMA engine reads the data from the receive
FIFO and writes it to external memory, one packet at a time per endpoint.
4. At the end of every packet write on the AHB to external memory, the transfer size for the endpoint
is decremented by the size of the written packet.
5. The OUT Data Transfer Completed pattern for an OUT endpoint is written to the receive FIFO on
one of the following conditions.
• The transfer size is 0 and the packet count is 0.
• The last OUT data packet written to the receive FIFO is a short packet (0 < packet size < maximum
packet size)
6. When either the application or the DMA pops this entry (OUT Data Transfer Completed), a Transfer
Completed interrupt is generated for the endpoint and the endpoint enable is cleared.
15.4.4.2.2.11 Generic Isochronous OUT Data Transfers Using Periodic Transfer Interrupt Feature
This section describes a regular isochronous OUT data transfer with the Periodic Transfer Interrupt
feature.
To initialize the core after power-on reset, the application must follow the sequence in Overview:
Programming the Core (p. 246) . Before it can communicate with the host, it must initialize an endpoint
as described in Endpoint Initialization (p. 281) . For packet writes in Slave mode, see: Packet Read
from FIFO in Slave Mode (p. 290) .
Application Requirements
1. Before setting up ISOC OUT transfers spanned across multiple frames, the application must allocate
buffer in the memory to accommodate all data to be received as part of the OUT transfers, then
program that buffer’s size and start address in the endpoint-specific registers.
• The application must mask the USB_GINTSTS.INCOMPLP (Incomplete ISO OUT).
• The application must enable the USB_DCTL.IGNRFRMNUM
2. For ISOC transfers, the Transfer Size field in the USB_DOEPx_TSIZ.XFERSIZE register must be a
multiple of the maximum packet size of the endpoint, adjusted to the DWORD boundary. The Transfer
Size programmed can span across multiple frames based on the periodicity after which the application
wants to receive the USB_DOEPx_INT.XFERCOMPL interrupt
• transfer size[epnum] = n * (mps[epnum] + 4 - (mps[epnum] mod 4))
• packet count[epnum] = n
• n > 0 (Higher value of n reduces the periodicity of the USB_DOEPx_INT.XFERCOMPL interrupt)
• 1 =< packet count[epnum] =< n (Higher value of n reduces the periodicity of the
USB_DOEPx_INT.XFERCOMPL interrupt).
3. In DMA mode, the core stores a received data packet in the memory, always starting on a DWORD
boundary. If the maximum packet size of the endpoint is not a multiple of 4, the core inserts byte
pads at end of a maximum-packet-size packet up to the end of the DWORD. The application will not
be informed about the frame number and the PID value on which a specific OUT packet has been
received.
4. The assertion of the USB_DOEPx_INT.XFERCOMPL interrupt marks the completion of the
isochronous OUT data transfer. This interrupt does not necessarily mean that the data in memory
is good.
• On USB_DOEPx_INT.XFERCOMPL, the application must read the endpoint’s Transfer Size
register to calculate the size of the payload in the memory.
• Payload size in memory = application-programmed initial transfer size - core updated final transfer
size
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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