EFM32WG Datasheet, PDF (533/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

...the world's most energy friendly microcontrollers
control of e.g. 3-channel BLDC or PMAC motors possible using only a single timer, see Figure 20.24 (p.
533) .
Figure 20.24. TIMER Overview of Dead-Time Insertion Block for a Single PWM channel
DTFALLT
DTRISET
Original PWM (TIM0_CCx_pre)
Select
HFPERCLKTIMERn
Clock cont rol Count er
=0
Prim ary out put (TIM0_CCx)
Com plem ent ary Out put (TIM0_CDTIx)
The DTI unit is enabled by setting DTEN in TIMER0_DTCTRL. In addition to providing the
complementary outputs, the DTI unit then also overrides the compare match outputs from the timer.
The DTI unit gives the rising edges of the PWM outputs and the rising edges of the complementary
PWM outputs a configurable time delay. By doing this, the DTI unit introduces a dead-time where both
the primary and complementary outputs in a pair are inactive as seen in Figure 20.25 (p. 533) .
Figure 20.25. TIMER Polarity of Both Signals are Set as Active-High
Original PWM
TIM0 _CC0
TIM0 _CD TI0
dt1
dt2
Dead-time is specified individually for the rising and falling edge of the original PWM. These values
are shared across all the three PWM channels of the DTI unit. A single prescaler value is provided
for the DTI unit, meaning that both the rising and falling edge dead-times share prescaler value. The
prescaler divides the HFPERCLK_TIMERn by a configurable factor between 1 and 1024, which is set in the
DTPRESC field in TIMER0_DTTIME. The rising and falling edge dead-times are configured in DTRISET
and DTFALLT in TIMER0_DTTIME to any number between 1-64 HFPERCLK_TIMER0 cycles.
20.3.3.1 Output Polarity
The value of the primary and complementary outputs in a pair will never be set active at the same time by
the DTI unit. The polarity of the outputs can be changed however, if this is required by the application. The
active values of the primary and complementary outputs are set by two the TIMER0_DTCTRL register.
The DTIPOL bit of this register specifies the base polarity. If DTIPOL =0, then the outputs are active-high,
and if DTIPOL = 1 they are active-low. The relative phase of the primary and complementary outputs is
not changed by DTIPOL, as the polarity of both outputs is changed, see Figure 20.26 (p. 534)
In some applications, it may be required that the primary outputs are active-high, while the
complementary outputs are active-low. This can be accomplished by manipulating the DTCINV bit of
the TIMER0_DTCTRL register, which inverts the polarity of the complementary outputs relative to the
primary outputs.
Example 20.1. TIMER DTI Example 1
DTIPOL = 0 and DTCINV = 0 results in outputs with opposite phase and active-high states.
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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